Interfacial Intermetallic Layer Growth Rates in Surface Mount Assemblies

Kinetics

During liquid solder reflow, substrate copper dissolves directly into the molten tin to establish the initial metallurgical bond, leaving behind an interfacial intermetallic compound (IMC) layer as the joint cools. This liquid-solid reaction forms scallop-shaped Cu6Sn5 (eta-phase) within 30 to 90 seconds spent above the alloy liquidus temperature. Later thermal exposure sets off secondary solid-state diffusion, which grows a planar Cu3Sn (epsilon-phase) sublayer between the base copper metallization and that original Cu6Sn5 band.

Interfacial Reflow Phase Formation

When reflowing SAC300 (Sn96.5Ag3.0Cu0.5) or SAC405 (Sn95.5Ag4.0Cu0.5) alloys at peak temperatures between 235°C and 250°C, molten tin strips pad copper at rates exceeding 0.1 micrometers per second. As the interface supersaturates, Cu6Sn5 nucleates heterogeneously across the copper surface. Fluid convection and local concentration gradients leave this freshly solidified boundary distinctly scalloped, producing an initial post-reflow intermetallic thickness typically between 0.8 and 1.8 micrometers, depending on peak temperature and time above liquidus (TAL).

SAC300 reflow peak temperature at 245°C for 60 seconds generates an initial Cu6Sn5 layer thickness between 1.1 and 1.8 micrometers.

Solid State Diffusion Equations

Once the joint solidifies, further interfacial growth shifts from convection-driven liquid reactions to solid-state lattice and grain-boundary diffusion. Total intermetallic thickness builds over time with thermal exposure, following classic parabolic growth:

x(t) = x0 + (D t)^n

where x(t) represents total intermetallic thickness at time t, x0 is initial post-reflow thickness, D is the effective interdiffusion coefficient, and n is the time exponent. If volume diffusion through the intermetallic lattice controls the reaction, n equals 0.5. Drops toward n = 0.33 indicate grain-boundary diffusion, which occurs regularly below 100°C when available thermal energy cannot activate bulk interstitial vacancies.

Activation Energy and Parabolic Kinetics

The temperature dependence of the interdiffusion coefficient D follows an Arrhenius relationship:

D = D0 exp(-Q / (R T))

where D0 is the frequency factor, Q is the apparent activation energy for IMC growth, R is the universal gas constant (8.314 J/mol·K), and T is absolute temperature in Kelvin. For lead-free tin-silver-copper formulations on bare copper substrates, measured activation energies for total interfacial IMC growth span 75 to 105 kJ/mol (approximately 0.78 to 1.09 eV).

Thin intermetallic layers preserve joint ductility, whereas thick layers reduce dynamic impact tolerance across operational lifespans.

Alloy

Substrate metallization chemistry governs interfacial reaction rates by altering phase composition, diffusion barriers, and crystal nucleation dynamics. Bare copper with organic solderability preservatives (OSP) promotes rapid Cu-Sn phase evolution, while electroless nickel immersion gold (ENIG) or electroless nickel electroless palladium immersion gold (ENEPIG) introduces a nickel barrier that suppresses copper migration into the solder bulk.

Substrate Surface Finish Metallurgy

On ENIG pad finishes, molten solder dissolves the gold flash layer within milliseconds. Microalloying additions alter interface compound structure. Liquid tin reacts directly with the nickel-phosphorus matrix to produce Ni3Sn4 intermetallic structures.

Because nickel diffusion into tin proceeds substantially slower than copper diffusion into tin, initial Ni3Sn4 growth rates are 60 to 80 percent lower than Cu6Sn5 growth rates on raw copper under identical reflow profiles. Continuous diffusion of nickel away from the deposit converts the surface region of the plating into an amorphous nickel-phosphorus layer (Ni3P), which introduces brittle fracture pathways when phosphorus concentrations exceed 12 atomic percent.

Microalloying Additions and Growth Suppression

Doping SAC alloys with trace elements alters interfacial phase growth during long-term storage. Adding 0.05 weight percent nickel or 0.02 weight percent cobalt stabilizes the Cu6Sn5 hexagonal crystal lattice, preventing low-temperature phase transformations into monoclinic structures at room temperature. Bismuth additions (2.0 to 4.0 weight percent) lower the melting temperature and reduce solid-state copper diffusion rates through lattice distortion, effectively curbing Cu3Sn growth during high-temperature aging cycles.

At What Rate Does Copper Diffusion Consume Substrate Metallization?

Copper substrate consumption correlates directly with total intermetallic growth thickness. Every micrometer of Cu6Sn5 formed consumes 0.43 micrometers of solid substrate copper. Formation of Cu3Sn consumes 0.66 micrometers of underlying copper per micrometer of growth.

High thermal loads can completely consume thin copper trace foils (such as 0.5-ounce copper, nominal thickness 17.5 micrometers) on high-density interconnect designs, leading to trace necking, resistance spikes, and total electrical open failures.

• Scallop coarsening describes the ripening process where large Cu6Sn5 grains absorb smaller adjacent crystals during extended liquid reflow, increasing surface roughness at the solder interface.
• Phosphorus accumulation occurs on ENIG finishes as nickel reacts with tin, concentrating unreacted phosphorus into a brittle Ni3P layer along the barrier boundary.
• Epsilon phase precipitation involves solid-state conversion of Cu6Sn5 into Cu3Sn along the copper interface, driven by vacancy concentration differences at temperatures exceeding 100°C.
• Gold embrittlement occurs when dissolved gold concentrations in the solder joint exceed 3 weight percent, precipitating brittle AuSn4 crystals within the primary intermetallic zone.

Thicker initial IMC layers indicate complete wetting during assembly, yet they narrow mechanical shock margins under accelerated life testing.

Heat

Thermal acceleration tests, including high-temperature storage life (HTSL) protocols per JESD22-A103, force rapid intermetallic phase transformations to evaluate long-term mechanical survival. Isothermal aging between 125°C and 150°C simulates multi-year operating exposure within condensed timeframes, revealing structural degradation mechanisms in surface mount assemblies.

Isothermal Aging and High Temperature Storage

Solder joints subjected to isothermal aging exhibit a distinct two-layer intermetallic architecture on copper finishes. The upper Cu6Sn5 layer grows slowly after solidifying, while the lower Cu3Sn layer thickens continuously by consuming copper from the substrate and tin from the overlying Cu6Sn5 phase. Beyond 500 hours of exposure at 125°C, Cu3Sn thickness often exceeds that of the remaining Cu6Sn5 layer, fundamentally shifting joint failure modes from bulk solder ductility to interfacial cleavage.

Solder joints aged under active thermal strain grow interfacial compounds faster than those stored in passive high temperature ovens.

Thermal Cycling and Mechanical Strain Interactions

Thermomechanical strain generated by coefficient of thermal expansion (CTE) mismatches between electronic components and printed circuit board substrates accelerates interdiffusion rates. Cyclic mechanical stress induces localized lattice dislocations and grain refinement within the interfacial region, lowering the activation energy barrier for atomic transport. Solder joints mounted on thick, rigid FR-4 sub-assemblies demonstrate up to 35 percent faster IMC growth rates under temperature cycling (-40°C to 125°C) compared to unstressed control samples aged at equivalent mean temperatures.

The exact threshold at which stress relaxation through solder creep ceases to relieve intermetallic strain energy remains unresolved under combined high-humidity and thermal cycling regimes.

Voiding

Differential diffusion flux between atomic species across interfacial boundaries creates microscopic lattice vacancies. Copper diffuses through Cu3Sn toward Cu6Sn5 significantly faster than tin diffuses toward the copper substrate. This imbalance, known as the Kirkendall effect, causes vacancy supersaturation and void nucleation directly along the Cu/Cu3Sn interface during thermal storage.

Kirkendall Vacancy Coalescence Mechanics

Kirkendall voids nucleate as sub-micron cavities (typically 100 to 500 nanometers in diameter) within the Cu3Sn layer or along its boundary with substrate copper. Extended thermal exposure causes individual vacancies to coalesce into continuous planar void networks. Impurities in the electrodeposited copper plating, such as sulfur, carbon, and organic brightener residues from board fabrication lines, act as preferential nucleation sites, accelerating voiding kinetics by up to two orders of magnitude.

Field emission scanning electron microscopy reveals Kirkendall voids co-locating directly along the interface between copper substrate and epsilon-phase intermetallic.

Mechanical Shear and Drop Shock Embrittlement

Planar Kirkendall void networks degrade mechanical toughness under dynamic shock loading, such as standard drop-shock testing defined by JESD22-B111. While high-density voiding may only minimally impact low-strain quasi-static shear strength, impact shock energy cannot dissipate through plastic deformation within the thin intermetallic zone. Failure paths transition abruptly from ductile bulk solder shear to catastrophic brittle interfacial cleavage along the void-riddled Cu3Sn/Cu interface.

1. Mount the thermal cycle test vehicle inside the environmental chamber at 125°C for 500 hours.
2. Extract sample boards and mount in epoxy resin following IPC-TM-650 Method 2.1.1.
3. Polish the cross-section using diamond suspension down to 0.05 micrometer particle size.
4. Measure Cu3Sn void density across a 100-micrometer linear interface using field-emission scanning electron microscopy at 10000x magnification.
5. Reject the assembly lot if vacancy planar area fraction exceeds 15 percent of the interfacial length.

Accepting PCB lots with high organic brightener levels in the plated copper causes widespread brittle joint detachment during consumer shipping, triggering total batch recalls after final distribution.

Analysis

Accurate quantification of interfacial intermetallic growth requires destructive metallographic cross-sectioning paired with advanced electron optics. Polishing artifacts mask true intermetallic boundaries. Precise mechanical preparation techniques prevent smear artifacts from soft lead-free solder onto hard intermetallic compounds, preserving true boundary geometry for thickness measurements.

Sample Preparation and Metallographic Cross Sectioning

Sectioning electronic packages requires slow-speed diamond saws with cold epoxy encapsulation to prevent thermal artifacts during cutting. Final polishing uses diamond suspensions down to 0.25 micrometers, followed by colloidal silica (0.05 micrometers) under light pressure. Chemical etching reveals underlying phase boundaries.

Brief chemical etching using a 2 percent ammonium persulfate solution or a dilute nitric-acid-alcohol mixture provides optical contrast between Cu6Sn5, Cu3Sn, and adjacent copper metallization.

Electron Microscopy and Energy Dispersive Spectroscopy

Scanning electron microscopy (SEM) operated in backscattered electron (BSE) mode yields phase contrast based on atomic weight variance. Quantitative chemical verification relies on energy dispersive X-ray spectroscopy (EDX) line scans or point analyses. Line profiles across the interface identify distinct atomic ratio steps corresponding to Cu6Sn5 (60 atomic percent Cu, 40 atomic percent Sn) and Cu3Sn (75 atomic percent Cu, 25 atomic percent Sn).

• Potted mounting media choice requires room-temperature curing acrylics or low-viscosity epoxies to eliminate thermal expansion stresses during encapsulation.
• Etching reagent selection dictates contrast clarity between contiguous intermetallic phases without over-etching the softer bulk solder alloy.
• Magnification calibration baseline mandates using certified micro-grid standards at identical working distances during field-emission SEM imaging.
• Phase identity confirmation relies on EDX spot analysis to distinguish intermediate phases from non-equilibrium ternary mixtures.

Per IPC-TM-650 Method 2.1.1, microsection evaluations must include minimum 10 thickness measurements across a 100-micrometer linear interface segment, using the calculated mean as the reported lot release metric.

Loss

Interfacial growth kinetics translate directly into financial liabilities through field failure rates, warranty reserve requirements, and shortened operating lifespans. Unchecked intermetallic growth degrades long-term mechanical reliability, turning small manufacturing defects into substantial commercial exposures across product deployments.

Warranty Exposure Calculations and Field Life Limits

To quantify financial risk where thin copper traces risk total dissipation, engineering groups calculate maximum allowable IMC growth over design operational lifespans. Consider an automotive ECU design operating continuously at 105°C ambient temperature with a 10-year design life target (87,600 operating hours). Using Arrhenius kinetics derived from SAC300 baseline parameters (D0 = 3.2 x 10^-7 m²/s, Q = 87.4 kJ/mol):

D = (3.2 x 10^-7) exp(-87,400 / (8.314 378.15)) = 2.65 x 10^-19 m²/s

t = 3.15 x 10^8 seconds (10 years)

x(t) = x0 + sqrt(D t) = 1.25 µm + sqrt((2.65 x 10^-19) (3.15 x 10^8)) = 1.25 µm + 9.14 µm = 10.39 µm total IMC

A total intermetallic thickness of 10.39 micrometers consumes roughly 5.2 micrometers of underlying copper substrate. On a high-density board utilizing 0.5-ounce copper plating (17.5 micrometers nominal thickness), solid-state intermetallic growth consumes approximately 30 percent of the trace cross-sectional area over 10 years, increasing localized conductor resistance and generating elevated thermal hotspots that accelerate thermal degradation.

Solder Volume and Pad Geometry Margins

Mitigating financial loss requires optimizing pad finishes and solder alloy selection prior to tooling sign-off. Transitioning high-reliability designs from bare copper OSP to ENEPIG finishes adds an upfront fabrication cost of roughly $0.08 to $0.15 per decimeter squared. This investment lowers solid-state intermetallic growth rates by over 60 percent, extending projected joint failure thresholds well beyond standard warranty windows.

Managing thermal profiles, specifying microalloyed solder alloys, and enforcing metallographic microsection audits during standard lot acceptance steps prevent premature interfacial failures, securing product reliability across demanding operational environments.