Arrhenius Solid State Diffusion Parameters for Lead Free PCB Surface Finishes

Interface

Lead-free surface finishes undergo solid-state atom migration whenever elevated temperatures energize the boundary between printed circuit board copper traces and deposited metallic coatings. This thermal motion drives intermetallic compound growth even during room temperature storage, accelerating during reflow, bake cycles, and high-temperature operating life. Quantifying this atomic flux relies on the Arrhenius kinetic model, where the diffusion coefficient D scales exponentially with absolute temperature T in Kelvin, governed by the pre-exponential frequency factor D0 and the activation energy Ea relative to the universal gas constant R (8.314 J/mol·K):

D(T) = D0 · expleft(-fracEaR · Tright)

Solid-state intermetallic layer thickness x increases over dwell time t according to parabolic growth kinetics where x = sqrtD · t or x2 = x02 + 2 · k · t, where k represents the reaction rate constant. Across lead-free surface finishes, distinct diffusion couples generate varied intermetallic compound structures with specific kinetic parameters. Electroless Nickel Immersion Gold (ENIG), Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), Immersion Tin, Immersion Silver, and Lead-Free Hot Air Solder Leveling (HASL) each yield distinct boundaries that govern solderability retention and mechanical joint fatigue.

The activation energy defines how sensitive the diffusion rate is to thermal excursions. Immersion Tin applied over bare copper exhibits a low activation energy of 79.1 kJ/mol for Cu6Sn5 formation, causing rapid consumption of pure surface tin during storage at 40circC or standard assembly preheating. When the temperature exceeds 100circC, the secondary phase Cu3Sn emerges at the copper interface with an activation energy of 103.4 kJ/mol.

This higher energy barrier makes Cu3Sn growth negligible during room storage but dominant during burn-in testing and automotive engine-compartment service.

Diffusivity values alter assembly survival. An engineer balancing assembly yields against storage lifetime calculates these migration parameters before setting shelf-life policies or wave soldering profiles. Thin surface deposits expose bare underlying copper once free tin transitions fully into intermetallic phases, terminating wetting capability during SMT reflow.

Layer

Plated deposits act as physical barriers that alter atomic migration speeds between underlying copper tracks and surface solder joints. In Electroless Nickel Immersion Gold finishes, electroless nickel co-deposited with 7 to 10 percent phosphorus by weight functions as a barrier against rapid copper dissolution. The gold topcoat (0.025 to 0.05,μm) serves solely to prevent nickel oxidation and dissolves into molten solder within two seconds of reflow, bringing liquid solder into direct contact with the nickel-phosphorus deposit.

Under elevated thermal aging, nickel atoms diffuse outward into tin to form crystalline Ni3Sn4, expelling co-deposited phosphorus into adjacent unreacted nickel to form an amorphous Ni3P barrier layer.

Phosphorus concentration drives structural transformation at this boundary. As nickel migrates toward tin, phosphorus accumulates at the intermetallic front, forming a thin, brittle phosphorus-rich deposit (Ni3P) alongside a hyper-phosphorus phase (NixP). This phase transformation reduces shear strength under high strain rate loading, such as board drop tests or thermal shock cycling.

Lower phosphorus contents below 6 percent accelerate nickel diffusion and intermetallic growth, while phosphorus concentrations above 10.5 percent create excessive stress, promoting hyper-corrosion during gold immersion plating, known on workshop floors as black pad defect.

Phosphorus Accumulation and ENEPIG Palladium Dynamics

Adding an electroless palladium deposit (0.05 to 0.15,μm) between nickel and gold creates the ENEPIG structure, which suppresses atomic flux. Palladium slows nickel dissolution into molten solder, shifting intermetallic growth from binary Ni3Sn4 to ternary (Pd,Ni)Sn4 and (Ni,Pd)3Sn4 phases. The activation energy for metal diffusion through the palladium barrier increases to 84.2 kJ/mol, reducing intermetallic formation speed to less than one-third that of standard ENIG under identical 125circC aging conditions.

Immersion Tin finishes omit barrier layers entirely, placing tin in direct contact with copper. Atomic diffusion across this copper-tin boundary proceeds rapidly. Copper diffuses into tin faster than tin diffuses into copper, generating an unequal mass transport flux.

This asymmetry generates localized tensile stress within the tin layer, inducing tin whisker growth that short-circuits fine-pitch components.

• Phosphorus Content Control ~ Maintaining bath phosphorus between 7.5 and 9.0 percent weight suppresses brittle Ni3P phase growth during secondary reflow operations.
• Palladium Thickness Window ~ Depositing 0.08 to 0.12,μm of palladium prevents full dissolution during SMT reflow while preventing brittle PdSn4 needle precipitation in solder joints.
• Immersion Tin Thickness Floor ~ Applying a minimum of 1.0,μm pure tin ensures at least 0.4,μm unreacted metallic tin remains after six months of storage at 30circC and 60 percent relative humidity.
• Immersion Silver Barrier Mechanism ~ Metallic silver dissolves completely into solder matrix, leaving a direct Cu-Sn boundary that grows Cu6Sn5 intermetallics during thermal cycling.

Plating suppliers occasionally claim that thin gold layers protect underlying nickel from diffusion indefinitely. Floor inspections show that immersion gold contains micro-porosity through which atmospheric oxygen reaches nickel, or through which tin diffuses during warm storage, rendering solderability claims based on gold thickness alone invalid.

Diffusivity

Transport of atoms through solid crystal lattices proceeds via bulk interstitial vacancies and grain boundary pathways. At temperatures below 100circC, grain boundary migration dominates atomic transport because the lower activation energy along disorganized crystal boundaries requires less thermodynamic energy than moving atoms directly through the ordered crystal matrix. Above 125circC, lattice volume migration increases significantly, altering overall intermetallic compound growth rates.

Isothermal Intermetallic Growth Model Assumptions

Predicting intermetallic growth across lead-free surface finishes requires setting baseline parameters. Assume a bare copper substrate coated with 1.2,μm Immersion Tin subjected to high-temperature storage at 125circC (398.15 K). At this temperature, the diffusion coefficient for copper into tin is 1.02 × 10-15 m2/s.

The growth of the total intermetallic layer (Cu6Sn5 + Cu3Sn) follows parabolic kinetics where initial intermetallic thickness x0 after initial reflow equals 0.3,μm.

The total intermetallic thickness x(t) after exposure time t = 1000 hours (3.6 × 106 seconds) is calculated as follows:

x(t) = sqrtx02 + 2 · k · t

x(1000 h) = sqrt(0.3 × 10-6 m)2 + 2 · (1.02 × 10-15 m2/s) · (3.6 × 106 s)

x(1000 h) = sqrt9.0 × 10-14 + 7.344 × 10-9 = sqrt7.34409 × 10-9 m2 ≈ 2.71,μm

Subtracting initial intermetallic thickness (0.3,μm) leaves 2.41,μm of grown intermetallic compound. StoiChiometric consumption calculations show that 1.0,μm of Cu6Sn5 intermetallic consumes approximately 0.84,μm of pure tin surface layer. Consuming 2.41,μm of intermetallic requires 2.02,μm of pure tin, exceeding the initial 1.2,μm tin deposit.

Consequently, free tin is fully consumed before 1000 hours at 125circC, exposing intermetallic compounds directly to air and rendering the PCB un-solderable.

Kirkendall Void Nucleation Kinetics

Imbalanced diffusion fluxes generate microstructural defects. Within the Cu-Sn system, copper atoms diffuse outward into Cu6Sn5 faster than tin atoms diffuse inward toward the copper substrate (DCu > DSn). This net flux of matter toward the solder joint leaves excess atomic vacancies behind at the Cu-Cu3Sn interface.

When vacancy concentrations exceed thermodynamic equilibrium, these vacancies coalesce into Kirkendall voids.

Does Palladium Thickness Arrest Intermetallic Growth Rates?

Increasing palladium deposit thickness in ENEPIG beyond 0.2,μm slows nickel intermetallic growth, but introduces mechanical failure modes. Dense palladium concentrations produce localized PdSn4 brittle intermetallic plates during reflow, which migrate into solder joint bulk material and act as stress concentrators during shock loads.

Whether grain boundary diffusion suppression can be achieved without destabilizing solder joint shear resistance remains an open question in board reliability engineering.

Incubation

Thermal exposures during board storage, transit, and multi-pass SMT reflow accumulate irreversibly within surface finish materials. Storing printed circuit boards in non-climate-controlled warehouses in humid tropical regions accelerates low-temperature solid-state diffusion. Storage at 35circC and 80 percent relative humidity over nine months consumes up to 0.5,μm of pure surface tin on Immersion Tin finishes, shifting baseline solderability profiles before boards reach assembly lines.

Reflow Thermal History and Intermetallic Multiplication

Double-sided SMT assembly subjects initial surface finish interfaces to multiple heating cycles. Peak reflow temperatures reaching 245circC to 260circC melt SAC305 solder, causing liquid-state dissolution rates that exceed solid-state diffusion speeds by four orders of magnitude. Liquid tin dissolves substrate copper at rates exceeding 0.1,μm/second.

During cooling, intermetallic compounds solidify as scallop-shaped Cu6Sn5 crystals. Secondary reflow passes reheat these initial structures to 250circC, smoothing scallop geometries into planar layers while driving secondary solid-state diffusion of copper inward to form Cu3Sn. Every reflow pass adds 0.2 to 0.4,μm of intermetallic thickness, reducing available pure surface tin for component leg wetting.

IPC-4552B specifies that mean electroless nickel deposit thickness must remain between 3.0 and 6.0,μm, with gold thickness held strictly between 0.05 and 0.10,μm to prevent severe mechanical embrittlement.

Environmental Aging and Solderability Degradation

As intermetallics consume topcoat metals, surface finishes lose protective capabilities. Immersion Silver finishes do not form thick intermetallics during room storage, but silver atoms migrate along surface sulfur pathways, forming Ag2S tarnish films that act as thermal barriers during soldering. OSP (Organic Solderability Preservatives) degrade via thermal oxidation when exposed to repeated reflow passes, losing protective organometallic polymers and exposing underlying copper to air oxidation.

Ignoring solid-state diffusion rates when establishing PCB stock aging policies results in un-solderable boards, elevated scrap rates, lost production time, rework charges, and potential latent field failures from brittle interface fractures.

Screening

Verification of solid-state diffusion control requires strict analytical testing of incoming bare boards and post-reflow assemblies. Standard inspection tools like X-ray Fluorescence (XRF) measure coating thickness but cannot evaluate microstructural diffusion phases, grain boundaries, or sub-micron intermetallic layers. Micro-sectioning combined with high-resolution Scanning Electron Microscopy (SEM) and Energy Dispersive Spectroscopy (EDS) provides necessary elemental profiling across intermetallic boundaries.

Laboratory Cross-Sectioning and SEM/EDS Diagnostics

Accurate cross-section analysis requires precise sample preparation to avoid smearing soft tin or gold over hard intermetallic compounds. Micro-section polishing uses diamond suspensions down to 0.05,μm, followed by brief chemical etching (typically 1 percent nitric acid in ethanol) to delineate grain boundaries and intermetallic interfaces.

SEM examination at 5,000× to 20,000× magnification enables direct measurement of total intermetallic thickness, identification of scallop morphology versus planar layers, and detection of sub-micron Kirkendall voiding. EDS line scans cross-sectioning the joint map spatial concentrations of copper, nickel, tin, phosphorus, and palladium, confirming whether phosphorus accumulation at ENIG interfaces remains below critical embrittlement levels.

Ball Shear and Mechanical Joint Testing Protocols

Mechanical testing validates intermetallic structural integrity under physical load. High-speed ball shear testing (operating at shear speeds of 1.0 to 4.0 meters/second per JESD22-B117) evaluates brittle-to-ductile fracture transitions in solder joints. Low-speed shear tests often mask interfacial embrittlement by shearing through soft solder bulk, whereas high-speed testing forces fractures along intermetallic layers, exposing weak Ni3P or Kirkendall void arrays.

1. Confirm plating thickness on incoming PCB batches using calibrated XRF per IPC-4552B, recording gold, palladium, and nickel values across five test points per panel.
2. Solder sample SAC305 test spheres to dedicated test coupons using standard reflow profiles with peak temperatures held at 245circC ± 3circC.
3. Subject test samples to accelerated isothermal aging at 150circC for 168 hours inside a dry nitrogen storage oven.
4. Execute high-speed ball shear tests at 3.0 m/s impact velocity, recording peak force to failure and failure mode distribution.
5. Accept batches only when ductile force modes exceed 95 percent of test samples, with zero total brittle fractures along intermetallic interfaces.

Under standard supply agreements referencing IPC-6012 Class 3, any PCB lot showing intermetallic thickness exceeding 0.8,μm in the as-received, un-reflowed state gives the buyer the right to reject the lot at supplier expense.

Liability

Solid-state diffusion failures often surface late in production, emerging as field warranty claims months after assembly. Latent solder joint failure caused by Kirkendall voiding or phosphorus embrittlement leads to catastrophic field operation failures. Tracing root causes requires isolating bare PCB manufacturing parameters from assembly reflow thermal profiles.

Commercial Risk Allocation and Warranty Defensability

Cross-border supply agreements must clearly define solid-state degradation boundaries. Bare board fabricators routinely dispute warranty claims on aged boards by asserting improper assembly warehouse storage or excessive reflow thermal profiles. Conversely, assembly operators attribute wetting failures to sub-specification initial coating thicknesses or contaminated plating baths.

Defending claims requires maintaining documented thermal histories from panel fabrication through final component soldering. PCB fabricators must supply lot-specific coating thickness records, phosphorus content analysis, and micro-section reports with every shipment. Assemblers must log storage environmental conditions and reflow thermal profiles for every SMT line run.

A clear rule of thumb for cross-border electronics procurement is that bare boards with Immersion Tin finishes should be assembled within ninety days of plating, while ENIG and ENEPIG finishes maintain solderability for up to three hundred sixty-five days when stored below thirty degrees Celsius and sixty percent relative humidity.

When field failures occur due to intermetallic embrittlement, financial liability rests on whether initial manufacturing parameters met specified tolerances. If bare board plating met IPC thickness standards, but assembly profiles exposed boards to three reflow passes and extended burn-in testing, financial responsibility shifts to the assembly contractor. If plating logs show phosphorus levels exceeding 10 percent or gold deposits below 0.03,μm, liability for board replacement, component scrap, and assembly rework returns to the PCB fabricator.

Managing shelf life by FIFO stock rotation and enforcing strict incoming analytical testing prevents latent intermetallic defects from reaching end customers, protecting operational budgets and field product reliability.