Quantifying Interfacial Solid State Diffusion Rates in Lead Free Solders

Slice

Grinding a printed circuit board assembly through a 0.4-millimeter pitch ball grid array requires precise micro-structural sectioning to expose the interfacial metallurgical boundary without smearing soft solder across hard copper substrates. A polished mount prepared on a diamond-lap wheel in a Kunshan laboratory reveals the exact condition of the joint immediately following reflow. The initial compound layer forms during the molten phase within seconds, establishing a baseline thickness between 0.5 and 1.5 micrometers.

Accurately tracking solid-state diffusion during later thermal storage or field operation requires an unblemished starting plane. Excessive cutting pressure deforms the soft tin-rich matrix, hiding micro-voids and inducing mechanical twinning that distorts electron backscatter diffraction measurements.

Sectioning starts by encapsulating the assembly in a low-exotherm, low-viscosity epoxy resin. Standard potting compounds that cure at elevated temperatures or generate significant exothermic heat drive extra solid-state aging during sample preparation, ruining the baseline measurement. Epoxy curing must remain under 40 degrees Celsius over a twelve-hour window.

Once set, diamond wafering saws cut the sample at low rotational speeds under continuous hydrocarbon coolant flow. Water-based lubricants cause galvanic corrosion across the tin-copper interface, leaving surface etching that masks structural defects under scanning electron microscopy.

Preparing the interfacial region follows a strict grinding and polishing sequence to preserve interfacial planarity:

1. Silicon carbide abrasive paper down to 1200 grit reduces section roughness while keeping applied mechanical pressure below four newtons per square centimeter.
2. Diamond suspension polishing on woven silk cloths at 3-micrometer and 1-micrometer steps removes grinding gouges without creating relief between the hard intermetallic layer and soft bulk solder.
3. Final mechanical-chemical polishing using 0.04-micrometer colloidal silica suspension at a pH of 9.5 surfaces the intermetallics for crystal lattice analysis.
4. Ultrasonic bath cleaning in pure isopropyl alcohol for ninety seconds removes residual silica particles from sub-micron interfacial cavities.

Selective chemical etching reveals individual compound phases without stripping delicate copper-tin intermetallics. A solution containing two percent hydrochloric acid in ethanol exposes the outer grain structure of the tin-rich bulk solder while leaving interfacial compounds intact. For high-resolution grain boundary analysis, an ammonium persulfate wash selectively attacks the copper substrate, isolating the intermetallic layer as a three-dimensional topography.

Skipping this step leaves the analyst dependent on flat two-dimensional section views that misrepresent true layer volume and interfacial surface roughness.

When factory quality teams present optical micrographs to prove joint integrity, those images frequently fail to distinguish the primary intermetallic compound from the underlying substrate. Optical resolution caps out near 200 nanometers, making early-stage solid-state diffusion layers impossible to measure accurately. The resident team inspects the actual sample mounts directly at the polish desk.

Soft tin smeared over the intermetallic boundary creates an illusion of a continuous, void-free bond, masking whether apparent interfacial splitting stems from sample preparation or thermal degradation.

Phase

Thermal exposure drives atomic exchange across the solder-substrate boundary, forcing stable crystalline compounds to nucleate and expand in the solid state. On bare copper substrates joined with tin-silver-copper alloys, two distinct intermetallic compounds form over time. Eta-phase copper-tin, expressed chemically as Cu6Sn5, forms adjacent to the bulk solder during reflow and continues growing via solid-state diffusion.

Epsilon-phase copper-tin, written as Cu3Sn, nucleates between the eta-phase and the copper substrate once prolonged elevated temperatures supply sufficient energy. The epsilon phase grows entirely in the solid state, consuming both the overlying eta-phase and the underlying copper substrate.

Epsilon Phase Formation at the Copper Boundary

Solid-state growth of the epsilon phase introduces structural vulnerability into the electronic assembly. Epsilon-phase material exhibits higher mechanical hardness and lower fracture toughness than either the surrounding eta-phase or the bulk solder alloy. As heat converts eta-phase material into epsilon-phase material, the volumetric balance shifts.

The denser crystal structure of the epsilon phase creates localized tensile stresses that concentrate along the substrate interface. High-reliability applications exposed to continuous operating temperatures above 85 degrees Celsius experience steady expansion of this brittle band.

Electroless nickel immersion gold finishes suppress copper diffusion by interposing a nickel barrier layer. Reflow creates a ternary intermetallic layer composed of nickel-copper-tin, typically identified as (Ni,Cu)6Sn5 or (Cu,Ni)3Sn4 depending on local copper concentrations in the solder bath. Solid-state aging on nickel substrates proceeds at lower atomic flux rates than on bare copper, but introduces phosphorus enrichment hazards.

Electroless nickel deposits contain six to ten weight percent phosphorus. As nickel migrates into the solder to build the intermetallic layer, rejected phosphorus accumulates at the interface, forming a brittle nickel-phosphorus compound layer known as the black pad zone.

A thick brittle intermetallic band concentrates thermal mechanical stress directly along the rigid substrate boundary.

Intermetallic Morphology under Continuous Thermal Stress

Scalloped structures formed during liquid-phase reflow gradually flatten into planar sheets during solid-state diffusion. This morphological shift alters how mechanical stress distributes across the joint under thermal cycling. Liquid reflow leaves behind rounded intermetallic scallops separated by tin-rich channels.

Solid-state heat exposure drives atomic diffusion that fills these channels, creating a continuous planar layer of uniform thickness. While a planar interface appears geometrically clean, it provides no mechanical interlocking against shear forces.

Structural failure modes shift predictably as solid-state diffusion alters the interfacial chemistry:

• Interfacial Brittle Cleavage propagates directly through the dense epsilon-phase layer under impact loading or severe drop testing.
• Kirkendall Micro-Voiding occurs within the epsilon-phase band when copper atoms diffuse toward the solder faster than tin atoms diffuse toward the substrate.
• Phosphorus Segregation Cracking detaches the intermetallic layer from nickel-plated pads along the hyper-passivated nickel-phosphorus plane.
• Bulk Solder Softening accompanies interfacial growth as thermal exposure coarsens internal precipitate structures and weakens matrix shear strength.

Cross-sectional evaluation of automotive control modules produced in Shenzhen showed total intermetallic thickness exceeding four micrometers after 1000 hours at 125 degrees Celsius. The epsilon phase accounted for more than forty percent of that total width. When thermal shock testing was applied, cracks originated within the epsilon layer rather than in the bulk solder.

The mechanical properties of the interface govern joint survival once solid-state diffusion transforms the initial reflow structure into a layered planar stack.

How does the microstructural state of the substrate grain structure alter the rate of intermetallic layer growth over multi-year operational cycles?

Flux

Quantifying interfacial solid-state diffusion requires isolating the kinetic constants that govern atomic transport across phase boundaries. Fick’s first law defines steady-state atomic flux across an interface as proportional to the concentration gradient of the diffusing species. In a solid solder joint, atomic flux depends directly on temperature, interdiffusion coefficients, and local vacancy concentrations.

Fick’s second law models non-steady-state conditions, describing how concentration changes over time during thermal aging.

Arrhenius Diffusion Kinetics and Growth Equations

Intermetallic layer growth in the solid state follows a parabolic relationship with time when the process is diffusion-controlled. The thickness of the intermetallic layer at time t is expressed by the standard parabolic growth equation: x = x0 + (k t)^0.5, where x represents total thickness, x0 is the initial reflow thickness, k is the growth rate constant, and t is time. The rate constant k varies exponentially with absolute temperature T according to the Arrhenius relationship: k = k0 exp(-Q / (R T)).

In this equation, k0 is the frequency factor, Q represents the activation energy for interdiffusion, and R is the universal gas constant.

Activation energy dictates how sensitive an alloy system is to temperature variations. Lower activation energy means diffusion accelerates rapidly with modest temperature increases. Calculating activation energy requires thermal aging experiments performed across at least three distinct temperatures, typically 125, 150, and 175 degrees Celsius.

Plotting the natural logarithm of the growth rate constant against the reciprocal of absolute temperature yields a straight line whose slope equals negative Q divided by R.

The tabulated data shows that eutectic tin-bismuth (Sn-58Bi) exhibits a significantly lower activation energy than SAC305. Low activation energy accelerates solid-state diffusion at lower absolute temperatures, causing substantial intermetallic growth even under mild operating conditions. Conversely, electroless nickel finishes elevate activation energy to 112.4 kilojoules per mole, establishing a robust kinetic barrier against rapid intermetallic expansion.

SAC305 on bare copper exhibits an activation energy of 84.3 kilojoules per mole for total intermetallic growth between 125 and 175 degrees Celsius.

Kirkendall Vacancy Generation Mechanics

Kirkendall voiding represents a direct failure of mass transport balance across the interfacial zone. In the copper-tin system, copper atoms diffuse out of the substrate into the epsilon-phase layer faster than tin atoms diffuse back into the copper lattice. This differential atomic flux produces a net transfer of matter away from the copper substrate.

To conserve lattice sites, vacancies migrate in the opposite direction, pooling along the interface between the substrate and the Cu3Sn intermetallic compound.

Sustained thermal exposure causes these vacancies to coalesce into microscopic voids ranging from 50 to 500 nanometers in diameter. High concentrations of vacancies reduce the effective contact area between the intermetallic layer and the copper pad. Under mechanical vibration or thermal shock, these void chains act as nucleation sites for high-speed crack propagation.

BGA components subjected to drop testing frequently fail along this voided interface, exhibiting clean separation with zero plastic deformation in the solder ball.

Impurities in the substrate material strongly influence Kirkendall void density. Sulfur, hydrogen, and carbon contamination present in electroplated copper pads accelerate vacancy condensation by lowering the nucleation energy barrier for void formation. High-purity copper plating baths containing organic levelers and brighteners leave trace organic residues embedded in the copper lattice.

During high-temperature aging, these trapped impurities break down, generating gas pockets that accelerate mechanical detachment under load.

Interfacial diffusion kinetics accelerate exponentially once operating temperatures cross two-thirds of the solder alloy melting point in absolute degrees Kelvin.

Bench

Measuring solid-state diffusion constants requires precise thermal aging matrices combined with calibrated electron microscopy imaging. A single aging temperature produces incomplete kinetic data. Standard test schedules isolate diffusion behavior by aging fully reflowed test coupons in convection ovens at 125, 150, and 175 degrees Celsius for intervals of 24, 100, 250, 500, and 1000 hours.

Ovens must maintain spatial temperature stability within plus or minus 0.5 degrees Celsius across all shelves to prevent thermal gradient errors in kinetic data.

Electron Microscopy and X-Ray Microanalysis Settings

Accurate measurement of sub-micron intermetallic layers demands scanning electron microscopy operated in backscattered electron imaging mode. Secondary electron imaging provides surface topography but lacks atomic number contrast, making it impossible to resolve the precise boundary between Cu6Sn5 and Cu3Sn. Backscattered electron imaging highlights density variations, rendering Cu6Sn5 as a medium-grey band and Cu3Sn as a darker grey band positioned between the primary compound and the copper substrate.

Energy-dispersive X-ray spectroscopy line scans verify the chemical stoichiometry of each layer. Accelerating voltage selection involves a critical tradeoff. An accelerating voltage of 20 kilovolts provides strong signal intensity for copper and tin K-alpha lines, but creates an electron interaction volume exceeding one cubic micrometer.

This interaction volume spans thin intermetallic layers, generating mixed elemental signals that falsely indicate phase blending. Lowering accelerating voltage to 12 kilovolts reduces interaction volume, allowing discrete stoichiometric identification of layers down to 300 nanometers in width.

JESD22-A103 Condition B specifies high temperature storage at 150 degrees Celsius for 1000 hours to quantify latent solid-state intermetallic growth.

Focused ion beam sectioning bypasses mechanical polishing artifacts entirely. A focused gallium ion beam cuts a precise trench through a single solder joint interface while leaving adjacent structures untouched. Platinum deposited via ion-assisted gas injection protects the top surface from curtaining artifacts during milling.

FIB cross-sections reveal true Kirkendall void distribution at 50,000 times magnification, exposing nanometer-scale vacancies that disappear under standard mechanical polishing due to solder smearing.

Checking factory aging dossiers demands systematic review of test conditions and instrument calibrations before accepting diffusion calculations:

• Thermal Stability Logs prove oven chambers maintained targeted temperatures without thermal spikes exceeding specified limits during long-duration runs.
• Magnification Calibration Certificates confirm SEM pixel scales match certified National Institute of Standards and Technology micro-scale standards within one percent accuracy.
• ETOH Etch Logs demonstrate sample preparation followed approved chemical exposure times to prevent artificial dissolution of the epsilon phase.
• Image Analysis Threshold Protocols document how image processing software defined phase boundary contrast lines during thickness measurement calculations.
• Multiple Point Measurement Sets verify intermetallic thickness was calculated from at least twenty random locations across five distinct joints per condition.

A review of a Dongguan module supplier’s failure analysis report showed zero Cu3Sn layer growth after 500 hours at 150 degrees Celsius. Inspection of the laboratory’s SEM setup revealed an accelerating voltage of 25 kilovolts combined with secondary electron detection. The broad interaction volume washed out contrast between the copper substrate and the epsilon phase, masking a 1.2-micrometer layer of Cu3Sn.

The factory cleared the batch based on optical inspection, forcing the buyer to absorb thirty thousand dollars in sorting and lab re-testing fees.

Shift

Micro-alloying strategies alter solid-state diffusion rates by modifying grain boundary energy and disrupting atomic transport paths within the solder matrix. Addition of minor alloying elements in quantities under 0.1 weight percent retards intermetallic growth, suppresses Kirkendall voiding, and stabilizes phase structures during elevated-temperature service. Dopants act either by precipitating along phase boundaries or by substituting directly into the intermetallic crystal lattice.

Dopant Mechanisms in Lead-Free Formulations

Nickel additions to SAC alloys substitute for copper in the Cu6Sn5 crystal lattice, forming (Cu,Ni)6Sn5. This substitution alters the lattice parameters and reduces thermodynamic driving forces for further copper dissolution. The modified lattice acts as a diffusion barrier, slowing down atomic flux across the interface.

Cobalt doping operates through a similar mechanism, concentrating at the intermetallic boundary to form a refined, stable layer that hinders solid-state growth during long-term storage.

Bismuth additions lower the melting point of tin-based solders while altering bulk diffusion kinetics. Bismuth exhibits low solid solubility in tin, segregating to tin grain boundaries during cooling. This grain boundary concentration blocks fast diffusion paths, reducing mass transport toward the interfacial region.

Phosphorus addition in low concentrations suppresses oxidation and refines intermetallic grain size, although excessive phosphorus drives brittle black pad formation on nickel finishes.

The performance table demonstrates that cobalt doping achieves the highest growth suppression, reducing intermetallic layer expansion by 41 percent compared to undoped SAC305. Cobalt also achieves a 75 percent reduction in Kirkendall void density after 500 hours at 150 degrees Celsius. Conversely, phosphorus addition increases void density by 15 percent, illustrating the risk of improper dopant selection.

Micro-alloying additions under 0.05 weight percent suppress solid-state diffusion rates by clogging high-velocity grain boundary migration paths.

Substrate modifications complement solder-side micro-alloying. Applying electroplated nickel-tungsten or nickel-vanadium alloy coatings creates dense crystalline barriers that reduce copper diffusion to near-zero levels. These barrier coatings maintain thermal integrity even under continuous operating temperatures exceeding 175 degrees Celsius, making them ideal for high-power electronics and under-hood automotive systems.

According to IPC-4552B requirement section 3.2.5, nickel deposit thickness on ENIG surfaces must maintain a minimum threshold of 3.0 micrometers to prevent complete nickel consumption during multi-pass reflow and subsequent solid-state storage.

Ledger

Translating diffusion kinetics into commercial risk management requires placing concrete monetary values on latent joint degradation. Standard assembly contracts assign supplier responsibility for defects discovered during initial automated optical inspection or functional testing. Solid-state diffusion defects, however, escape factory gates completely.

Kirkendall voids and brittle epsilon-phase growth manifest months after shipment, triggering field failure costs that easily exceed the landed value of the original circuit board assemblies.

A supplier contract in the Yangtze River Delta cluster must explicitly specify thermal aging validation thresholds as part of batch release criteria. Solder joint specifications based solely on initial post-reflow cross-sections leave buyers fully exposed to latent field returns. Solder joint acceptance clauses should define maximum allowable intermetallic growth rates and void area percentages following a standardized 500-hour aging protocol at 150 degrees Celsius.

Incorporate the following quantified parameters directly into supply agreements for high-reliability assemblies:

Maximum total intermetallic compound thickness must remain under 4.0 micrometers following 500 hours of storage at 150 degrees Celsius. Epsilon-phase thickness cannot exceed 1.2 micrometers under the same thermal exposure. Interfacial Kirkendall void area, calculated from backscattered electron SEM cross-sections, must remain below eight percent of total interfacial length.

Any lot failing these metrics triggers immediate engineering hold, full root-cause analysis, and supplier-funded replacement of affected inventory.

Calculating field reliability pricing requires factoring in warranty reserve funds against calculated diffusion rates. Assemblies operating in elevated ambient thermal environments degrade at predictable speeds. When a factory substitutes a cheap Sn-Cu binary solder for a specified SAC305 alloy with nickel micro-alloying, the parabolic growth rate constant shifts from 1.2 x 10^-18 to 9.8 x 10^-18 square meters per second.

That order-of-magnitude increase in growth rate reduces predicted joint operational lifespan from ten years down to eighteen months. The initial unit cost savings of three cents per board generates a potential warranty exposure exceeding forty dollars per unit in field replacement costs.

Audit rights must extend directly to the supplier’s metallographic testing partners. Contractual clauses specifying quality audits are worthless if the factory subcontracts long-term reliability aging to unaccredited third-party laboratories. Quality agreements should restrict thermal aging and SEM evaluations to ISO/IEC 17025 accredited facilities using verified energy-dispersive X-ray spectroscopy calibration standards.

Field failures originating from unverified intermetallic growth inevitably land on the buyer’s balance sheet unless structural diffusion limits are written into the original procurement dossier.