Quantifying Kirkendall Microvoid Accumulation and Interfacial Degradation in SAC305 Assemblies
Excessive organic plating bath additives accelerate copper vacancy coalescence, creating planar Kirkendall microvoid seams that cause brittle drop shock failure.
Pad
Cross-sectional inspection of fallen ball grid array packages routinely reveals planar separation directly at the boundary between copper substrate traces and the intermetallic compound layer. When SAC305 (96.5% tin, 3.0% silver, 0.5% copper) alloy solidifies over copper, metallurgical bonding initially produces a scalloped Cu6Sn5 intermetallic film. Solid-state exposure to operating temperatures between 100°C and 150°C triggers continuous diffusion across that boundary.
Copper atoms exit the substrate toward the solder volume at a rate roughly three times higher than the reverse flux of tin into copper. This lattice-flux imbalance leaves behind vacant atomic sites within the copper lattice.
Vacancies consolidate into sub-micron cavities along the interface between Cu3Sn and copper. These vacancies represent the classic Kirkendall effect in solid-state metallurgy. As thermal aging advances past 500 hours at 125°C, isolated microvoids merge into extensive planar seams.
Solder joints subjected to sudden kinetic stress shear cleanly along this porous plane. The bulk SAC305 solder ball remains undamaged on the component side while the circuit board pad retains only bare intermetallic remnants.
Thinner intermetallic compounds retain mechanical ductility while thicker interfacial layers generate severe stress concentrations.
Field data from electronic assemblies deployed in automotive powertrains and industrial drives demonstrate that interfacial degradation exhibits distinct characteristics compared to thermal fatigue cracking. Fatigue cracking traverses the bulk solder along grain boundaries under repeated thermomechanical expansion. Interfacial degradation severs the base connection under minimal mechanical strain.
- Interfacial Planar Shearing happens along the Cu3Sn to Cu interface during drop impact tests rather than shearing through bulk solder.
- High Resistance Drift manifests as progressive milliohm increases across power distribution pins prior to complete mechanical dislodgement.
- Premature Package Detachment occurs during secondary assembly processes when boards flex under press-fit connector installations.
- Uneven Pad Consumption displays localized pitting across copper pads where electroplating bath brighteners concentrated during circuit board fabrication.
Brittle joints crack under minimal impact. When a facility encounters board assemblies failing drop shock qualification after standard thermal bake cycles, engineers frequently mistake the failure for poor reflow wetting. Modifying reflow profiles to extend time above liquidus accelerates the initial Cu6Sn5 growth without resolving underlying vacancy coalescence.
Solder joint integrity remains compromised as long as rapid copper consumption proceeds unmitigated during operating service.
True operational reliability hinges on maintaining structural pad density under extended thermal stress.
Plating
Substrate electrodeposition baths introduce trace chemical impurities that dictate the velocity of vacancy coalescence. During printed circuit board manufacturing, electrolytic copper baths utilize organic additives, leveling agents, and brighteners such as bis(3-sulfopropyl) disulfide to ensure uniform copper distribution across blind microvias and surface pads. Residual sulfur, carbon, and chlorine co-deposit into the copper matrix at concentrations measuring between 10 and 80 parts per million.
These non-metallic impurities act as heterogeneous nucleation sites for vacancy condensation.
Clean copper halts planar vacancy condensation. When copper contains less than 5 parts per million of total sulfur and carbon, vacancies generated by unequal atomic diffusion migrate toward grain boundaries or sink into surface dislocations without organizing into continuous voids. High-purity rolled annealed copper foils exhibit minimal void development even after 1,000 hours of aging at 150°C. Conversely, electroplated copper deposits laden with organic breakdown products display dense bands of microvoids within the Cu3Sn layer after 200 hours under identical conditions.
| Plating Bath Formulation | Additive Class | Deposit Sulfur Content | Deposit Carbon Content | Mean Microvoid Density | Interfacial Shear Failure Rate |
|---|---|---|---|---|---|
| High-Speed Acid Copper Sulfate | Disulfide Brightener System | 38 ppm to 55 ppm | 45 ppm to 70 ppm | 18.4 voids per 100 µm | 92% |
| Standard Acid Copper Sulfate | Low-Organic Leveler System | 12 ppm to 20 ppm | 18 ppm to 28 ppm | 6.2 voids per 100 µm | 24% |
| Direct-Current Pyrophosphate Bath | Inorganic Complexing Agent | 2 ppm to 4 ppm | 5 ppm to 10 ppm | 1.1 voids per 100 µm | 4% |
| Methanesulfonic Acid Bath | Polyalkylene Glycol Carrier | 4 ppm to 7 ppm | 8 ppm to 15 ppm | 1.8 voids per 100 µm | 6% |
Organic additives leave carbon residue. Plating chemistry dictates void density. Printed circuit board suppliers often run electroplating baths at maximum additive concentrations to boost deposition speed and maximize panel throughput.
The resulting copper deposit appears visually flawless and passes initial solderability testing per IPC J-STD-003 without incident.
- Total Organic Carbon Analysis reveals additive breakdown accumulation within the copper plating tank before contamination levels affect copper crystalline orientation.
- Secondary Ion Mass Spectrometry pinpoints sulfur and chlorine concentrations trapped inside electroplated surface pads down to parts-per-billion sensitivity.
- Transmission Electron Microscopy evaluates nanotwinned copper structures to confirm whether plating grain sizes resist rapid atomic diffusion.
- High Temperature Aging Screen verifies pad resistance to microvoid formation by subjecting raw plated coupons to 150°C for 168 hours prior to solder assembly.
Why Do Plating Impurities Destabilize Intermetallic Bonds?
Foreign atomic species alter the local chemical potential at the advancing intermetallic boundary. As copper atoms dissolve into the growing Cu3Sn layer, insoluble sulfur and carbon atoms cannot integrate into the Cu3Sn crystal lattice. These rejection solutes segregate to the Cu/Cu3Sn interface.
Segregated impurities lower the free energy barrier required for vacancy nucleation, allowing microvoids to form under minimal vacancy supersaturation.
Cross sections tell the truth. Microvoids align along impurity segregation zones rather than dispersing randomly through the intermetallic phase. When challenged with cross-sectional micrographs of microvoid bands, circuit board fabricators typically claim that their chemistry suppliers guarantee standard bath additives and that interfacial voids originate purely from standard solder alloy physics.
Evolution
Thermodynamic drivers govern intermetallic layer thickening alongside vacancy aggregation throughout operating exposure. During initial reflow at peak temperatures between 235°C and 250°C, molten SAC305 dissolves copper rapidly until reaching chemical equilibrium. Upon cooling, Cu6Sn5 forms with a scalloped morphology measuring roughly 1.5 to 2.5 microns in height.
Solid-state exposure subsequent to reflow causes a second intermetallic layer, Cu3Sn, to nucleate between the base copper and the Cu6Sn5 layer.
The epsilon layer expands relentlessly. As aging progresses, Cu3Sn grows at the expense of Cu6Sn5 and the copper substrate. At 150°C, the diffusion coefficient of copper through Cu3Sn is approximately 1.0 × 10⁻¹³ cm²/s, whereas the diffusion coefficient of tin through Cu3Sn is approximately 3.0 × 10⁻¹⁴ cm²/s.
This substantial difference in atomic mobility sustains a steady vacancy flux directed into the copper substrate boundary.
What Accelerates Interfacial Voiding during Thermal Storage?
Temperature elevation increases atomic mobility exponentially according to Arrhenius kinetics, whereas mechanical stress state influences the condensation of vacancies into physical microcavities. Microvoid diameter ranges between 0.1 and 0.8 microns in early development stages, visible only through field emission scanning electron microscopy. Extended exposure transforms individual spherical microcavities into elongated lenticular voids that occupy upwards of 40% of the total linear interfacial boundary.
| Aging Time at 150°C | Mean Cu6Sn5 Thickness | Mean Cu3Sn Thickness | Total Intermetallic Layer | Microvoid Area Fraction | Void Count per 100 µm Line |
|---|---|---|---|---|---|
| 0 Hours (As Reflowed) | 1.85 µm | 0.25 µm | 2.10 µm | 1.2% | 0.8 |
| 100 Hours | 2.40 µm | 0.85 µm | 3.25 µm | 4.5% | 3.5 |
| 250 Hours | 2.95 µm | 1.60 µm | 4.55 µm | 12.8% | 8.2 |
| 500 Hours | 3.45 µm | 2.45 µm | 5.90 µm | 26.4% | 17.6 |
| 1,000 Hours | 3.90 µm | 3.80 µm | 7.70 µm | 43.1% | 28.4 |
| Measurements taken via backscattered electron imaging on polished metallographic cross sections at 10,000x magnification. | |||||
Quantifying vacancy accumulation requires examining the volume of copper consumed against intermetallic layer growth. Assume a ball grid array pad with a diameter of 400 microns subjected to 150°C isothermal aging. Solder volume is 0.035 cubic millimeters.
After 500 hours, metallographic evaluation records a Cu3Sn layer thickness increase of 2.2 microns across the pad contact area of 1.257 × 10⁻⁷ square meters.
Calculating the volume of Cu3Sn formed yields 2.765 × 10⁻¹³ cubic meters. Based on the molar volume of Cu3Sn (32.8 cm³/mol) versus copper (7.11 cm³/mol), synthesizing one mole of Cu3Sn consumes three moles of copper. The corresponding copper volume consumed equals 1.80 × 10⁻¹³ cubic meters, which corresponds to a linear copper substrate consumption depth of 1.43 microns across the pad.
A measured vacancy volume exceeding fifteen percent of total consumed copper indicates severe organic contamination within substrate plating.
Atomic flux calculations indicate that copper atoms depart the substrate at a rate leaving a net vacancy flux of approximately 1.2 × 10¹⁴ vacancies per square centimeter per second at 150°C. In high-purity substrates, bulk lattice dislocations absorb these vacancies without void formation. Under sulfur contamination levels exceeding 30 ppm, nucleation site saturation occurs within 100 hours. The resulting microvoid accumulation proceeds along the Cu3Sn/Cu boundary until effective metallic contact area drops below critical fracture thresholds.
Thermal aging exposes the flaw. The inspection window closes fast. How subtle shifts in ambient humidity and board surface finishes alter vacancy supersaturation during sub-100°C long-term operations remains an ongoing debate among assembly reliability engineers.
Rupture
Mechanical degradation along the solder pad boundary becomes fatal under dynamic loading conditions. While static ball shear testing performed per JESD22-B117A at low shear speeds (0.1 millimeters per second) allows plastic deformation of bulk SAC305 to mask interfacial weakness, high-speed impact loading reveals catastrophic embrittlement. Testing joints at speeds between 500 and 3,000 millimeters per second forces failure along the weakest microstructural zone before bulk solder can undergo plastic relaxation.
Copper moves faster than tin. Solder joints aged past 250 hours at 150°C shift their failure mode entirely under high-speed ball pull tests per JESD22-B115. As-reflowed solder joints exhibit ductile failure through the bulk solder ball, absorbing substantial fracture energy through plastic strain.
Solder joints carrying extensive microvoid arrays fail along the Cu/Cu3Sn interface with near-zero plastic deformation.
| Thermal Aging Duration (150°C) | Mean Fracture Energy | Ductile Bulk Failure | Mixed Mode Failure | Brittle Interfacial Failure |
|---|---|---|---|---|
| 0 Hours | 14.8 mJ | 96% | 4% | 0% |
| 100 Hours | 11.2 mJ | 68% | 22% | 10% |
| 250 Hours | 6.4 mJ | 24% | 31% | 45% |
| 500 Hours | 2.1 mJ | 2% | 11% | 87% |
| 1,000 Hours | 0.8 mJ | 0% | 3% | 97% |
Shear strength drops fifty percent. Vacancies gather along the substrate boundary. The rapid decline in mechanical toughness directly correlates with the coalesced microvoid area fraction measured along the boundary line.
When microvoids bridge more than 20% of the interfacial length, drop shock durability drops by an entire order of magnitude.
Interfacial voiding converts ductile solder connections into impact-sensitive release mechanisms under standard transit acceleration.
Brittle failure follows vacancy coalescence. Dynamic strain rates experienced during JEDEC JESD22-B111 board-level drop testing generate shock waves exceeding 1,500 G across mounted packages. Under these accelerations, mechanical stress concentrates directly along the porous microvoid planes.
Cracks propagate along coalesced microcavities, severing electrical continuity instantaneously across entire rows of corner solder balls.
Undetected interfacial voiding leads inevitably to field recalls when portable or vehicle-mounted electronics endure repeated handling shocks and vibration cycles in service environments.
Remedy
Suppression of Kirkendall microvoiding demands strict intervention across circuit board fabrication chemistry, surface metallurgy selection, and assembly thermal management. The most direct metallurgical barrier involves introducing minor alloying dopants into the solder paste or using substrate finishes that alter intermetallic diffusion kinetics. Adding nickel, bismuth, or cobalt to SAC solders modifies the intermetallic structure, retarding Cu3Sn layer growth and impeding vacancy formation.
Nickel surface finishes such as Electroless Nickel Immersion Gold (ENIG) or Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) eliminate the Cu/Cu3Sn interface entirely. The resulting Ni3Sn4 or (Cu,Ni)6Sn5 intermetallics exhibit balanced interdiffusion rates that do not produce Kirkendall voiding. For designs constrained to direct copper pads (such as Organic Solderability Preservatives or Immersion Silver), circuit board plating specifications must enforce rigorous controls on copper electrodeposition baths.
- Plating Additive Concentration Limits define specific operational thresholds for brightener and leveler concentrations verified via cyclic voltammetric stripping every shift.
- Secondary Ion Mass Spectrometry Screening mandates that lot acceptance testing on raw boards limits sulfur below 10 ppm and carbon below 20 ppm inside pad copper.
- Solder Alloy Dopant Control requires SAC305 paste with micro-additions of 0.05% nickel or 0.02% cobalt to suppress Cu3Sn intermetallic growth rates.
- Reflow Thermal Profile Restrictions cap total time above liquidus to 60 seconds and enforce peak temperatures below 245°C to limit initial intermetallic thickness.
Rework heats the joint twice. Batch tracking stops the bleeding. Manufacturing facilities running multiple reflow operations or hand soldering rework exacerbate vacancy formation.
Secondary heating cycles accelerate the transition of Cu6Sn5 into Cu3Sn, consuming more copper from already compromised plating deposits.
Technical purchase contracts must state that cross sections displaying more than ten percent microvoid coverage after one hundred sixty-eight hours at one hundred fifty degrees Celsius justify lot rejection.
Procurement agreements must incorporate IPC-4552 and IPC-6012 quality amendments stipulating that substrate deliveries failing the 168-hour thermal aging screening trigger immediate supplier quarantine and replacement obligations at the vendor’s expense.