Phase Field Simulation of Vacancy Migration and Kirkendall Void Coalescence in Advanced Micro Bumps
Phase field simulations predict Kirkendall void coalescence at micro bump interfaces, guiding plating bath controls and barrier layer metallurgy to prevent failure.
Mesh
Finite element discretizations of a twenty-micrometer copper pillar bump fail when the spatial grid exceeds twenty-five nanometers across the intermetallic boundary. Under thermal aging at one hundred fifty degrees Celsius, copper atoms diffuse into tin faster than tin replenishes the copper lattice. This flux imbalance generates an excess chemical potential of vacancies within the narrow copper-rich zone.
Phase field methods track this spatial evolution without explicit interface tracking by defining continuous field variables for atomic fractions, structural order, and vacant lattice sites. The local free energy density combines chemical contributions, gradient energy terms that penalize steep interfaces, and elastic strain energy arising from lattice mismatch between copper, eta-phase copper-tin intermetallic compound, epsilon-phase compound, and bulk solder.
Micro-bump geometry intensifies diffusion kinetics relative to conventional ball grid arrays. A solder volume under forty micrometers in diameter contains a minuscule total atomic reservoir. Interfacial reaction consumes up to eighty percent of the available solder mass during reflow and subsequent thermal stabilization.
The Cahn-Hilliard equation governs the conserved vacancy concentration field:
∂c_v / ∂t = ∇ · + S_v
Here, c_v denotes the local vacancy fraction, M_v represents the vacancy mobility tensor, F is the total system free energy functional, and S_v defines the net generation or annihilation rate from dislocation climb and interfacial grain boundaries. Simulating this equation across a standard micro-bump requires balancing numerical stability against physical diffuse interface widths. Setting the gradient energy coefficient too high artifically broadens the copper-to-intermetallic interface, which artificially smears the chemical potential peak where voids nucleate.
Discretization Bounds across Interfacial Layers
Numerical divergence occurs when the spatial step size exceeds half the physical interface width. For a diffuse interface thickness calibrated to one nanometer, grid dimensions along the diffusion coordinate must stay below 0.4 nanometers. Planar adaptive mesh refinement concentrates computational density along the moving reaction fronts of Cu6Sn5 and Cu3Sn while coarsening the grid within the unreacted copper seed layer and bulk solder core.
Planar shear strength drops forty-two percent when interfacial void volume fraction reaches eight percent of the total joint contact area.
Grid generation parameters dictate boundary capture precision. The solver tracks sharp phase transitions alongside diffuse vacancy sinks. Temporal steps follow an explicit Courant-Friedrichs-Lewy condition constrained by vacancy mobility, often demanding increments smaller than ten picoseconds during the earliest stages of thermal annealing.
| Parameter Description | Physical Symbol | Assigned Model Value | Engineering Unit |
|---|---|---|---|
| Interface Gradient Energy Coefficient | κ_c | 1.25 × 10⁻⁹ | J · m⁻¹ |
| Cu Diffusion Coefficient in Cu3Sn | D_Cu_ε | 5.40 × 10⁻¹⁶ | m² · s⁻¹ |
| Sn Diffusion Coefficient in Cu3Sn | D_Sn_ε | 1.20 × 10⁻¹⁷ | m² · s⁻¹ |
| Copper Lattice Mismatch Strain | ε_xx | 0.021 | dimensionless |
| Minimum Boundary Resolution | Δx_min | 0.35 | nm |
Simulations conducted without accounting for anisotropic mobility yield circular void morphologies absent in physical cross sections. Transmission electron microscopy reveals elongated, faceted planar voids along the copper-Cu3Sn interface. Phase field formulations integrate interfacial stiffness tensors to capture this crystallographic pinning.
The elastic energy contribution enters the variational derivative through the stress field, coupling local volume changes caused by vacancy condensation directly to mechanical constraints from the silicon die and organic substrate.
Solder
Lead-free micro bumps rely on tin-silver-copper alloys deposited via electroplating onto copper pillars capped with nickel or direct copper seed layers. The physical dimensions dictate intermetallic reaction rates that outpace bulk solder behavior. The diffusion rate of copper atoms through Cu3Sn exceeds that of tin atoms by more than an order of magnitude at operating temperatures between eighty and one hundred twenty-five degrees Celsius.
This directional flux differential forces vacancies to migrate toward the copper source to conserve crystal lattice sites.
Current density exacerbates this mass imbalance in flip-chip configurations. Advanced packaging designs push operational currents past 1.5 × 10⁴ amperes per square centimeter. Electromigration exerts an electron wind force that drives both interstitial atoms and lattice vacancies along the electron flow trajectory.
Cathode interfaces experience rapid atomic depletion, accelerating Kirkendall void agglomeration into continuous structural fissures.
Does Current Density Alter Vacancy Sink Strength?
Applied electrical fields alter vacancy sink and source dynamics by superimposing an electro-migration drift velocity on chemical diffusion. The modified flux expression combines chemical potential gradients, mechanical hydrostatic stress gradients, and electric field vectors:
J_v = – D_v ∇c_v – (D_v c_v / k_B T)
The effective charge number Z _v governs vacancy drift magnitude. Atomic drift directed toward the anode leaves the cathode deficient in lattice mass. Dislocation densities within the electroplated copper pillar act as primary vacancy sources, maintaining localized supersaturation adjacent to the intermetallic boundary.
Once supersaturation surpasses critical thermodynamic thresholds, embryonic voids stabilize against dissolution.
- Electromigration Current Polarization directs atomic flux toward the anode side, tripling vacancy concentration at the unpassivated cathode interface.
- Hydrostatic Tensile Stress Accumulation lowers the formation energy of vacancies, establishing stable nucleation sites within twenty nanometers of the Cu3Sn intermetallic band.
- Impurity Segregation Effects at grain boundaries alter interfacial energy, preventing vacancy annihilation at dislocation jogs.
IPC-A-610 qualification standards reject assembly lots showing continuous interfacial separation exceeding twenty-five percent of total micro-bump diameter.
Foundry electroplating chemistry controls copper deposit purity. Organic additives such as suppressors, accelerators, and levelers degrade during plating operations. Breakdown products, predominantly sulfur, carbon, and chlorine fragments, incorporate into the copper pillar lattice.
These codeposited impurities alter vacancy annihilation efficiency by pinning dislocations. Impurity-rich copper pillars exhibit Kirkendall void densities four times greater than ultra-pure electrolytic deposits following two hundred hours of thermal baking.
Factory engineers in regional packaging facilities frequently argue that minor organic additive drift inside the electroplating bath remains acceptable as long as height uniformity across the wafer meets standard deviation limits.
Pit
Lattice defects condense into visible micropores when local vacancy saturation exceeds the equilibrium limit by a factor of three. In phase field theory, this condensation is captured by coupling the conserved concentration field to an unhampered structural order parameter, η, defining the transition between intact solid and empty pore. The value η = 1 denotes dense crystalline solid, whereas η = 0 defines a fully formed void.
The interface between the void and surrounding intermetallic tracks the Allen-Cahn dynamic equation:
∂η / ∂t = – L_η
The kinetic coefficient L_η governs pore boundary mobility. The local free energy contains a double-well potential with respect to η, creating an energetic barrier separating solid from void states. Vacancy supersaturation tilts this potential, making the zero-density state thermodynamically favorable when atomic extraction removes mechanical lattice support.
What Volume Fraction Triggers Interfacial Fracture?
Finite element simulations coupled to phase field outputs reveal that void volume fraction correlates directly with mechanical compliance degradation. Coalescence transforms distributed nanometer-scale pores into planar cracks. Individual vacancies first form clusters containing fewer than fifty atomic sites.
These clusters grow by absorbing incoming vacancy fluxes driven by the chemical potential gradient between the copper pillar and the intermetallic front.
Pore coalescence accelerates once mean void spacing drops below the average pore diameter. When two neighboring diffusion zones overlap, the free energy of the intervening solid neck increases due to heightened interface curvature and localized stress concentration. The system minimizes total surface energy by dissolving the neck, joining two spherical voids into an elongated micro-crack.
This morphology mirrors structural degradation observed in physical cross-sections prepared through focused ion beam milling.
| Annealing Duration | Mean Pore Radius | Interfacial Coverage | Measured Fracture Toughness |
|---|---|---|---|
| 100 Hours | 12.4 nm | 3.1 % | 2.10 MPa · m¹/² |
| 250 Hours | 28.6 nm | 7.8 % | 1.65 MPa · m¹/² |
| 500 Hours | 64.2 nm | 14.9 % | 1.12 MPa · m¹/² |
| 1000 Hours | 148.0 nm | 28.4 % | 0.48 MPa · m¹/² |
Elastic energy terms in the phase field model dictate void coalescence pathways. Micro bumps sit trapped between thick silicon chips and stiff organic substrates, preventing free thermal expansion. Mismatch in thermal expansion coefficients produces triaxial tensile stress during cool-down cycles from reflow temperatures of two hundred forty degrees Celsius.
Tensile stress lowers the energy barrier for void formation along interfaces perpendicular to the stress axis.
Void coalescence velocity accelerates nonlinearly once individual pore perimeters touch adjacent grain boundary intersections.
Phase field models predict that randomly nucleated voids align into continuous planes when normal tensile stress exceeds eighty megapascals. The planar alignment concentrates subsequent vacancy flux along a single two-dimensional path rather than distributing porosity throughout the intermetallic volume. This localized coalescence creates catastrophic failure planes under mechanical shock testing.
Micro bumps subjected to high-g drop tests fail through this planar void sheet at displacement levels eighty percent below pristine baseline joints.
Unresolved questions persist regarding the exact thermodynamic influence of sub-ppm chlorine segregation on the interfacial surface energy term that regulates pore neck collapse.
Rework
Thermal assembly lines expose multi-die packages to cumulative reflow exposures that multiply vacancy generation. Rework operations add two to three additional thermal spikes reaching two hundred sixty degrees Celsius. Each heat cycle drives further copper dissolution into the intermetallic phase, consuming unreacted copper substrate and depositing fresh vacancy populations at the Cu3Sn interface.
Field failures traced to drop impact and thermal cycle fatigue frequently originate in reworked components rather than single-pass production units.
Accelerated life testing conditions establish reliability limits. Package qualification under JEDEC standard JESD22-A104 involves temperature cycling from minus forty to one hundred twenty-five degrees Celsius. Advanced micro bumps subjected to phase field validation must sustain two thousand cycles without electrical resistance increases exceeding ten percent.
Reworked packages consistently show resistance drift starting at eight hundred cycles, caused by pre-coalesced void networks formed during the secondary reflow profile.
- Multiple Reflow Cycles expand the brittle Cu3Sn layer thickness beyond two micrometers, exhausting primary vacancy annihilation sites in the base metal.
- Localized Underfill Curing Stress generates persistent peel stresses on corner bumps, focusing vacancy drift toward outer chip perimeters.
- Secondary Flux Activation Residue introduces ionic contaminants that accelerate boundary diffusion through unsealed package edges.
Field data confirms that secondary reflow profiles without precise peak temperature control double the void growth rate during downstream burn-in screening. Production yields collapse during temperature-humidity bias testing when micro-cracks breach the hermetic bump seal, allowing moisture ingress into the active silicon circuitry.
Remedy
Mitigating Kirkendall void formation requires direct intervention in plating metallurgy and interfacial barrier design. Standard bare copper pillars allow unrestricted diffusion into tin-rich solder. Depositing an electroplated nickel barrier layer between two and three micrometers thick suppresses copper dissolution.
Nickel reacts with tin to form (Ni,Cu)6Sn5, which displays a self-limiting growth rate nearly one order of magnitude slower than binary copper-tin intermetallics.
Doping electroplating chemistries modifies atomic kinetics directly. Introducing cobalt, zinc, or manganese dopants at concentrations between zero point one and zero point five weight percent alters interfacial thermodynamic potentials. Phase field models calibrated with cobalt-doped lattice parameters demonstrate that cobalt atoms segregate to intermetallic grain boundaries, blocking copper vacancy transport channels.
This mechanism suppresses Kirkendall pore nucleation even under prolonged high-temperature exposure.
Audit inspections across offshore packaging workshops demand rigorous control of chemical bath maintenance schedules. Plating bath additives decompose under continuous electrical charge transfer. Facilities that neglect carbon filtration cycles allow additive breakdown products to accumulate in the electroplated deposit.
Independent chemical assay verifies additive purity, preventing the inclusion of vacancy-nucleating sulfur compounds in the production stream.
| Under Bump Metallurgy | Primary IMC Phase | 1000h IMC Thickness | Kirkendall Void Susceptibility |
|---|---|---|---|
| Bare Cu Pillar | Cu6Sn5 / Cu3Sn | 3.8 μm | Severe |
| Cu / Electroless Ni / Immersion Au | (Ni,Cu)6Sn5 | 0.9 μm | Negligible |
| Cu Pillar with 0.2wt% Co Dopant | (Cu,Co)6Sn5 | 1.4 μm | Minimal |
| Electroless Ni / Electroless Pd / Immersion Au | (Pd,Ni)Sn4 / (Ni,Cu)6Sn5 | 0.7 μm | Low |
Procurement agreements must incorporate strict electroplating impurity caps and grain size criteria. Technical specifications should state that copper electroplating deposits shall maintain sulfur levels below ten parts per million and carbon levels below thirty parts per million as verified by secondary ion mass spectrometry.
Procurement contract addenda enforce batch rejection whenever interfacial shear testing reveals brittle cleavage along the intermetallic boundary before reaching forty-five megapascals of nominal shear force.