Solid State Intermetallic Growth Kinetics under Accelerated Thermal Aging Regimes

Bake

Convection chambers inside high-reliability facilities maintain continuous thermal dwells to simulate multi-year operational shelf storage. Test chambers running at one hundred twenty-five degrees Celsius or one hundred fifty degrees Celsius drive atomic diffusion across solid solder-substrate boundaries long after the initial liquid reflow pulse has solidified. The oven runs continuously.

The rate of lattice transformation depends on thermal activation energy, elemental concentration gradients, and the local defect density of the deposited base metal. When tin-based solders rest against copper leadframes or printed circuit board pads, solid-state reactions proceed without interruption throughout the burn-in period.

Thermal acceleration regimes compress years of ambient storage into hundreds of hours. Standard profiles specified under JESD22-A103 subject electronic assemblies to continuous temperatures ranging from one hundred degrees to one hundred seventy-five degrees Celsius. The elevated thermal floor gives copper and tin atoms sufficient kinetic energy to overcome vacancy migration barriers within the crystal lattice.

Tin atoms diffuse rapidly. Rather than stopping once a stable metallurgical seam forms, the solid-state reaction consumes bulk copper and bulk tin to thicken interfacial compounds continuously. Understanding this expansion is necessary for predicting field lifespans in automotive under-hood controllers, aerospace avionics, and industrial power switches.

Thicker initial intermetallic boundaries accelerate Kirkendall vacancy condensation during subsequent thermal storage.

Suppliers in high-volume manufacturing corridors often treat post-reflow inspection as the definitive sign of mechanical integrity. A solder joint that exhibits satisfactory wetting angles and excellent shear resistance on day three can degrade into a brittle, void-ridden boundary by month six if held at elevated operating temperatures. Copper migration leaves empty lattice sites.

Factory engineering teams frequently overlook solid-state growth rates during environmental qualification, assuming that intermetallic compound formation ceases once components exit the reflow furnace cooling tunnel. Solid-state diffusion operates under distinct thermodynamic and kinetic rules compared to liquid-solid wetting reactions. Denser grain structures resist void migration longer under thermal aging than coarse dendritic casts.

Phase

Molten solder dissolves surface copper during reflow, leaving a scalloped eta-crystal band along the boundary. Once the assembly cools and enters high-temperature storage, solid-state diffusion reorganizes this metallurgical zone into two distinct stoichiometric layers. Pure copper from the substrate reacts with Cu6Sn5 to form Cu3Sn, known as the epsilon phase.

This epsilon layer grows directly against the copper pad, while the eta phase remains positioned between Cu3Sn and the remaining bulk solder matrix. Copper content drops near the solder.

Thermodynamic Partitioning and Parabolic Evolution

The total intermetallic thickness follows a classic parabolic growth trajectory governed by diffusion-controlled kinetics. The thickness at any aging interval correlates with the square root of time multiplied by a temperature-dependent rate constant. The Arrhenius relationship defines this rate constant through the pre-exponential factor, the universal gas constant, absolute temperature, and the activation energy of the specific intermetallic system.

For lead-free alloys such as Sn96.5Ag3.0Cu0.5 reacting with bare copper, the combined activation energy for total layer thickening falls between seventy and eighty-five kilojoules per mole. Epsilon-phase formation exhibits an activation energy exceeding one hundred kilojoules per mole, meaning higher test temperatures skew the layer ratio heavily toward Cu3Sn.

Take a 35-micron copper trace on an automotive printed circuit board finished with organic solderability preservative, soldered with SAC305, and subjected to thermal aging at one hundred fifty degrees Celsius. The initial reflow produces a baseline intermetallic thickness of 1.2 microns composed almost entirely of Cu6Sn5 scallops. With an experimentally verified total growth rate constant of 8.45 multiplied by ten to the negative thirteen square centimeters per second, an aging exposure of five hundred hours adds 3.9 microns of solid-state intermetallic growth.

Total intermetallic thickness reaches 5.1 microns. More critically, the Cu3Sn sublayer expands from an imperceptible trace to a continuous 1.8-micron layer directly on the copper pad. Pure tin dissolves adjacent pad metal.

This structural transition consumes approximately 2.4 microns of pure copper from the trace, altering trace impedance and weakening the mechanical anchor point.

Total intermetallic thickness along the copper-tin interface expands beyond four micrometers after three hundred hours of exposure at one hundred fifty degrees Celsius.

Will Kirkendall Microvoiding Trigger Interface Delamination?

Lattice vacancy supersaturation develops when atomic species diffuse across an interface at unequal speeds. In the copper-tin solid-state diffusion couple, copper atoms diffuse into the tin-rich intermetallic lattice substantially faster than tin atoms diffuse back into the copper matrix. This imbalance produces a net outward flux of copper atoms, leaving behind unoccupied lattice sites along the Cu-Cu3Sn boundary.

Slower belt speeds increase thermal dwell. As thermal aging continues past two hundred hours at one hundred fifty degrees Celsius, these vacancies coalesce into microscopic voids measuring fifty to three hundred nanometers across.

The concentration of Kirkendall microvoids increases exponentially when the base copper contains electroplating impurities such as sulfur, carbon, or phosphorus. These codeposited contaminants segregate to the Cu3Sn interface, lowering the critical free energy barrier for void nucleation. Void coalescence cuts contact area.

Over extended aging durations, individual spherical vacancies merge into planar micro-fissures that reduce the effective contact area between the solder joint and the substrate pad. The factory floor manager asserted that furnace temperatures drifted because local power grid fluctuations during the third shift altered conveyor speeds.

Mount

Sample extraction from thermal racks follows strict mechanical sectioning guidelines to prevent introduced shear damage. Board-level interconnects subjected to accelerated aging regimes contain fragile, embrittled interfaces that fracture under diamond saw blade vibration if potted incorrectly. Cold-setting epoxy resins with low curing exotherms protect the metallurgical boundary from post-test thermal annealing during encapsulation.

The technician records furnace temperatures hourly. Grinding requires silicon carbide abrasive papers loaded with water lubricant, stepping systematically through grits from 320 to 4000 to maintain planar flatness without plucking intermetallic crystals from the softer bulk solder.

Cross-Sectional Preparation and Electron Microscopy Standards

Polishing demands automated mechanical heads running diamond suspensions graded from three microns down to one-quarter micron on low-nap synthetic cloths. Final surface finishing utilizes an alkaline colloidal silica suspension of 0.04-micron particle size to deliver damage-free surfaces suitable for backscattered electron imaging. Scanning electron microscopy operating between fifteen and twenty kilovolts enables compositional contrast, separating the dark gray substrate copper, the medium gray Cu3Sn band, the light gray Cu6Sn5 crystals, and the bright white solder matrix.

Accurate quantitative metallography avoids single-point measurements. True boundary morphology features local undulations, scallop peaks, and grain boundary grooves that skew one-off readings. Reliable measurement protocols apply continuous image analysis across a minimum boundary width of one hundred microns, calculating true volume-averaged thickness by dividing total intermetallic cross-sectional area by line length.

Failing to specify cross-sectional polishing grits down to one-quarter micron under IPC-TM-650 Method 2.1.1 causes false acoustic microscopy readings that pass micro-cracked solder joints.

Do Parabolic Rate Constants Predict Real Rupture?

Laboratory rate constants derived from pristine, coupon-level specimens frequently underestimate growth velocities observed in production hardware. Trace geometry, local solder volume, metallization roughness, and residual assembly stresses alter atomic mobility along grain boundaries. Surface diffusion along unconstrained edges proceeds faster than bulk lattice diffusion, creating localized intermetallic wedges that penetrate deeply into thin trace copper.

Cross sections expose hidden vacancies. Several structural indicators reveal premature aging failure before catastrophic board separation occurs:

• Interfacial void coalescence manifests as continuous dark seams tracing the boundary between Cu3Sn and the copper pad, indicating that vacancy saturation has degraded sixty percent or more of the shear area.
• Scallop detachment occurs when tin diffusion consumes copper necks bridging adjacent Cu6Sn5 crystals, releasing unanchored intermetallic particles directly into the bulk solder matrix.
• Complete barrier consumption reveals itself through localized breakthroughs where the solder alloy has dissolved nickel plating entirely and begun rapid solid-state attack on structural copper.
• Phosphorus segregation bands appear in electroless nickel coatings as dark lines directly beneath Ni3Sn4 compounds, signifying nickel depletion and structural embrittlement of the underlying pad.

Improper sample preparation destroys the boundary evidence and results in full container recalls after unverified assemblies ship across the Pacific.

Fracture

High-speed ball shear tools deliver dynamic lateral loads to reveal interfacial weaknesses in aged interconnects. As thermal storage extends, solder joint failure mechanics transition from ductile deformation within bulk solder to brittle fracture along intermetallic boundaries. Bulk solder alloys yield plastically, absorbing impact energy through dislocation motion and grain rotation.

Intermetallic compounds possess complex monoclinic or hexagonal crystal structures characterized by high hardness, negligible dislocation mobility at ambient temperatures, and minimal fracture toughness. Thermal stress concentrates at sharp corners. When an intermetallic layer exceeds four to five microns, applied shock loads concentrate stresses along flat phase boundaries rather than distributing them throughout the compliant bulk solder.

Mechanical Degradation and Failure Mode Shifts

High-speed shear tests conducted at speeds between five hundred millimeters per second and four thousand millimeters per second under JESD22-B117 differentiate sound solder joints from thermally degraded structures. Under quasi-static conditions, plastic creep in the bulk alloy masks brittle interfacial weaknesses. High-velocity testing prevents stress relaxation, forcing the crack path to follow the weakest mechanical link.

Brittle seams snap under drop impacts.

The data demonstrates a clear inflection point between two hundred fifty and five hundred hours of exposure. Beyond four microns of total intermetallic thickness, shear energy drops precipitously, losing over seventy percent of its baseline shock absorption capability. Brittle cleavage replaces ductile yielding.

Microscopic examination of fractured surfaces confirms that the crack path shifts from ductile dimpling inside the tin alloy to clean, planar cleavage running along the Cu3Sn-copper interface or within the Kirkendall void band.

Planar intermetallic layers crack under lower impact forces than scallop-shaped boundary structures because shear stresses concentrate uniformly along flat phase transitions.

Executing Interface Qualification Sequences

Verifying interfacial stability across multi-lot shipments requires standardized qualification workflows executed under strict environmental controls:

1. Baseline sampling records the initial post-reflow intermetallic thickness across five designated critical components per lot prior to environmental chamber loading.
2. Chamber placement positions test coupons within calibrated thermal zones exhibiting temperature uniformity within plus or minus two degrees Celsius across all test trays.
3. Periodic pull intervals extract designated sample subsets at two hundred fifty, five hundred, and one thousand hours for destructive metallurgical evaluation.
4. High-speed mechanical testing evaluates shear strength across thirty solder spheres per interval at a ram speed of one thousand millimeters per second.
5. Fractographic categorization determines the percentage of brittle interfacial fracture versus bulk ductile failure across all severed interconnect pads.

Adding Section 4.2 of JESD22-A103 into the purchase specification forces suppliers to calibrate thermocouples at three points across the chamber rack before aging tests commence.

Margin

Contract terms between offshore brand owners and assembly plants often treat thermal aging tests as formal documentation rituals. Standard factory quotes bundle environmental testing into overhead fees without detailing thermocouple placements, cross-section polish specifications, or void calculation algorithms. When qualification tests fail after four weeks in the chamber, rework options disappear.

Discarded printed circuit boards and scrapped surface-mount components quickly erase operating profits across international production runs. Tin enrichment accelerates crack paths.

Sourcing teams operating at a distance must defend mechanical reliability by writing explicit diffusion barriers and aging thresholds directly into commercial agreements. Relying on generic factory certifications creates false confidence, as standard factory quality audits evaluate present surface conditions rather than solid-state aging degradation. Suppliers naturally favor bare copper or cheap immersion tin finishes because surface preparation costs remain low.

Protecting mission-critical hardware demands precise procurement instructions:

• Nickel diffusion barrier thickness defines a mandatory electrolytic or electroless nickel deposit of three to five microns beneath gold or silver finishes to suppress copper migration.
• Maximum intermetallic growth caps mandate that aged samples shall not exceed five microns of total compound thickness after five hundred hours at one hundred fifty degrees Celsius.
• Interfacial void density limits establish that Kirkendall voiding shall occupy no more than ten percent of the linear interface observed at twenty thousand times magnification.
• Supplier audit access grants buyer engineering representatives physical access to thermal test chambers, calibration records, and metallographic polishing bays during validation runs.

Physical verification cannot be delegated to email updates. When production facilities in Shenzhen or Ningbo execute thermal testing, visiting the metallographic preparation room reveals testing rigor within ten minutes. Inspecting diamond polishing suspensions, wheel rotation speeds, and cross-section flatness exposes whether the factory measures genuine interfacial kinetics or simply produces unground, poorly focused images to satisfy paper milestones.

The engineering community continues to debate whether sub-micron dopant additions such as cobalt or nickel alter bulk intermetallic activation energy or merely delay initial vacancy clustering.