Meaning
Quality criteria in surface mount assembly documentation specify two-dimensional geometric thresholds for un-bonded area proportions within solder connections. SMT line engineers calculate planar void fraction to evaluate solder joint integrity beneath ball grid arrays and bottom-terminated components. Standard IPC-A-610 establishes maximum allowable cumulative void area percentages across total joint pad areas.
The metric governs solder paste reflow process validation and inspection approval, ending once solder joints pass non-destructive X-ray verification.
Measurement Computation
Automated X-ray inspection systems calculate void ratios by comparing dark solder regions against light un-bonded areas within a single focal plane. Digital image processing algorithms segment grayscale pixel intensity values across component pad boundaries. The total void area divided by the total pad area yields the planar percentage value for each termination.
Image resolution calibration ensures accurate detection down to sub-millimeter void dimensions.
Thermal Impact
Excessive voiding reduces effective heat transfer areas beneath power-dissipating semiconductor dies. Localized thermal resistance rises, raising junction temperatures during device operation. Reduced solder volume weakens joint fatigue resistance under cyclic mechanical stress.
High void ratios accelerate solder joint crack propagation during temperature cycling.
Threshold Requirement
Industry standard IPC-7095 limits total void area to twenty-five percent for standard ball grid array connections. Critical power electronics components frequently enforce stricter internal limits of fifteen percent or less. SMT production lines must adjust reflow temperature profiles and paste deposition parameters when measured values exceed specified limits.