Kirkendall Void Nucleation Mechanics in Electroplated Microbumps
Electroplated copper microbump voids nucleate when bath additive sulfur impurities catalyze vacancy condensation along the Cu-Cu3Sn boundary during thermal aging.
Bath
Electrodeposition tanks running acid copper sulfate chemistry deposit copper pillars across wafer lots destined for advanced packaging. Organic additives govern copper deposition rates across microbump cavities: bis(3-sulfopropyl) disulfide acts as an accelerator, polyethylene glycol functions as a suppressor, and Janus Green B operates as a leveler. Plating bath additives alter grain boundaries.
When direct electrical current drives cupric ions toward cathode surfaces, organic molecules break down under high cathodic overpotentials and incorporate trace elements directly into the growing metal lattice. Sulfur, chlorine, carbon, and nitrogen entrapment occurs simultaneously with copper reduction.
Chemical supply houses formulate proprietary additive packages to achieve void-free bottom-up filling of narrow lithographic openings. Secondary breakdown reactions generate thiols and sulfonates that adsorb on copper crystallites. Secondary ion mass spectrometry profiles reveal sulfur levels ranging from 5 parts per million up to 75 parts per million depending on bath age, cathodic current density, and brightener concentration.
Chlorine ions, maintained between 40 and 60 milligrams per liter to assist suppressor adsorption, codeposit alongside organic fragments. High current density spikes accelerate additive inclusion at pillar seed interfaces.
| Additive Formulation | Current Density (A/dm²) | Sulfur Content (ppm) | Carbon Content (ppm) | Chlorine Content (ppm) | Interfacial Void Fraction (%) |
|---|---|---|---|---|---|
| High-accelerator fresh makeup | 2.0 | 6.2 | 14.1 | 1.8 | 1.4 |
| Balanced standard production | 3.5 | 12.8 | 28.5 | 4.2 | 4.6 |
| Aged bath high-byproduct | 3.5 | 38.4 | 67.0 | 11.5 | 23.8 |
| High-leveler overdrive | 5.0 | 54.0 | 92.3 | 18.1 | 37.2 |
Impurity concentrations dictate metallurgical behavior during downstream assembly. Clean electrodeposited copper exhibits equiaxed grains that resist vacancy aggregation during solid-state diffusion. Elevated sulfur and carbon contents pin grain boundaries, restricting grain growth during the initial solder reflow cycle.
The resulting fine-grained columnar microstructures maintain high boundary density, creating rapid diffusion pathways for copper atoms migrating toward tin-rich solder caps.
Additive Turnover and Carbon Contamination Dynamics
Electrolyte maintenance across high-volume packaging lines requires disciplined chemical replenishment schedules. Cyclic voltammetric stripping tracks active additive concentrations, yet standard stripping methods evaluate collective electrochemical activity rather than individual molecular fragments. Anode oxidation splits disulfide bridges in accelerators, generating monomeric byproducts that bypass standard filtration systems.
- Total organic carbon monitoring verifies that additive breakdown byproducts stay below 2.5 grams per liter before electrochemical bath renewal.
- High-performance liquid chromatography analysis confirms exact accelerator-to-suppressor ratios twice per operating shift. This separation prevents runaway organic entrapment.
- Cathodic current ramp control regulates initial current strike levels, minimizing impurity entrapment at the underlying barrier metal layer.
- Bleed-and-feed dosing routines purge degraded organic fragments on a continuous schedule to maintain stable grain boundary impurity limits.
Carbonaceous deposits disrupt atomic packing along grain junctions. Transmission electron microscopy reveals segregated carbon clusters measuring 1 to 3 nanometers across columnar grain walls. Thermal energy supplied during flip-chip reflow mobilizes vacancies pinned by these impurity atoms.
Fresh copper deposits with fine columnar grains suppress vacancy mobility until high temperatures trigger grain growth.
Contaminated deposits appear specular and uniform under optical inspection. Solder cap plating proceeds over the copper pillar without visible wetting abnormalities, concealing interfacial chemical defects until solid-state aging begins. The electroplating engineer asserts that bright, uniform pillar surfaces indicate complete chemical stability across the entire wafer batch.
Lattice
Thermal exposure during assembly bakes initiates solid-state interdiffusion across the copper-solder interface. Copper diffuses faster than tin. As temperatures reach 150 to 200 degrees Celsius, copper atoms leave their original sites and move across the metallurgical boundary to react with tin atoms, producing intermetallic compound layers.
The epsilon phase grows nonlinearly. The consumption of copper generates two distinct intermetallic compounds: copper-rich Cu3Sn adjacent to the copper pillar, and tin-rich Cu6Sn5 facing the remaining solder volume.
Atomic movement across this bi-material couple does not balance. Copper possesses an intrinsic diffusion coefficient in Cu3Sn roughly three to eight times higher than the intrinsic diffusion coefficient of tin within the same intermetallic lattice. Tin atoms move toward the copper pillar at a sluggish pace while copper atoms migrate outward rapidly.
This unequal flux creates a net transfer of matter away from the copper base metal.
- Copper dissolution into liquid solder occurs during reflow, consuming 1 to 2 micrometers of copper to form initial scalloped Cu6Sn5 grains.
- Solid-state conversion to epsilon phase takes place as copper atoms diffuse through Cu6Sn5 grain boundaries, forming a planar Cu3Sn band underneath.
- Counter-flux vacancy injection generates excess crystallographic vacancies within the copper substrate immediately adjacent to the advancing Cu3Sn boundary.
- Vacancy supersaturation threshold crossing destabilizes the local metal matrix, causing vacancies to precipitate out of solution when local vacancy solubility limits collapse.
Darken-Kirkendall theory establishes that an unequal atomic flux produces an opposing vacancy flux. When copper atoms leave the substrate faster than tin atoms replace them, vacancies must flow across the Cu3Sn interface into the copper pillar to maintain volume equilibrium. If these incoming vacancies cannot find immediate sinks such as free surfaces or climbing dislocations, vacancy supersaturation develops rapidly within the first 500 nanometers of the copper boundary.
| Intermetallic Phase | Temperature (°C) | Diffusion Coefficient Cu (cm²/s) | Diffusion Coefficient Sn (cm²/s) | Intrinsic Flux Ratio (J_Cu / J_Sn) |
|---|---|---|---|---|
| Cu6Sn5 (η-phase) | 150 | 1.2 × 10⁻¹³ | 3.8 × 10⁻¹⁴ | 3.16 |
| Cu6Sn5 (η-phase) | 200 | 8.5 × 10⁻¹³ | 2.1 × 10⁻¹³ | 4.05 |
| Cu3Sn (ε-phase) | 150 | 5.4 × 10⁻¹⁴ | 8.1 × 10⁻¹⁵ | 6.67 |
| Cu3Sn (ε-phase) | 200 | 4.1 × 10⁻¹³ | 5.2 × 10⁻¹⁴ | 7.88 |
Vacancy Supersaturation and Interfacial Flux Imbalance
Intermetallic growth kinetics depend on temperature and boundary condition geometry. In conventional ball grid arrays with large solder volumes, the copper pad acts as an infinite source of atoms, allowing stable Cu6Sn5 scallop ripening. In 25-micrometer microbumps, solder volume restriction and high surface-to-volume ratios alter diffusion geometry.
Once tin consumption approaches completion, Cu6Sn5 converts progressively into Cu3Sn, consuming more copper per unit volume of intermetallic formed.
High temperature storage at 150 degrees Celsius produces an atomic flux imbalance where copper atom migration outpaces tin back-diffusion by a factor of three.
Atomic concentration gradients sustain the chemical driving force for copper migration. As Cu3Sn thickens beyond 1 micrometer, the diffusion path for copper atoms lengthens, yet the intrinsic flux disparity between copper and tin widens under sustained thermal input. The resulting net vacancy injection rate into the copper substrate exceeds the absorption capacity of natural crystalline defects, driving the system into a persistent supersaturated state that seeks energetic relaxation through void formation.
Defect
Cavity development within microbumps demands an understanding of heterogeneous nucleation mechanics. Diffusion vacancy flux drives voiding. Thermodynamic models show that homogeneous vacancy condensation requires vacancy supersaturation ratios exceeding fifty times the equilibrium thermal vacancy concentration.
Such extreme supersaturation levels do not materialize during standard operational thermal bakes. Heterogeneous nucleation sites provide the necessary reduction in the activation energy barrier for vacancy clustering.
Why Do Voids Condense near Copper Boundaries?
Impurities codeposited from electroplating additives lower the interfacial surface energy required to form a stable vacancy nucleus. Sulfur atoms, insoluble in solid copper at room temperature, segregate strongly to grain boundaries and interphase interfaces during thermal storage bakes. Sulfur segregation at the Cu/Cu3Sn boundary reduces the critical nucleus radius from 12 nanometers down to 1.8 nanometers.
Segregated sulfur atoms act as catalytic seeds where supersaturated vacancies coalesce without overcoming high strain energy barriers.
High-resolution analytical transmission electron microscopy reveals sulfur segregation along the faceted planes separating Cu3Sn grains from the underlying copper lattice. Voids coalesce into planar crevices. Chlorine atoms contribute similar catalytic effects by lowering local cohesive strength.
Pure rolled copper foils containing less than 1 part per million sulfur show no void nucleation after 1,000 hours of storage at 150 degrees Celsius, whereas electroplated copper with 25 parts per million sulfur develops dense void bands within 200 hours. The physical mechanism parallels vacancy condensation and grain boundary cavitation seen in high-pressure steam turbines in electrical power generation, where prolonged thermal stress drives micro-pore formation along pinned grain margins.
Take an assembly containing 20,000 microbumps distributed across an interposer with a 40-micrometer pitch. Assume an operating temperature of 105 degrees Celsius with a copper pillar sulfur concentration of 30 parts per million. Under these assumptions, published vacancy diffusion models project void nucleation initiation at 280 operating hours, with void areal coverage along the Cu/Cu3Sn interface reaching 25 percent by 1,200 hours.
If the sulfur concentration is held below 4 parts per million through strict bath controls, the calculated time to reach 25 percent interfacial void coverage extends beyond 22,000 hours under identical thermal assumptions.
A contested boundary exists regarding critical sulfur thresholds. Packaging literature frequently cites 10 parts per million as the safe operational ceiling for sulfur in electroplated copper pillars. This 10 parts per million limit rests on secondary ion mass spectrometry measurements published in 2008 examining large 100-micrometer solder balls subjected to isothermal aging at 150 degrees Celsius.
In modern 15-micrometer microbumps carrying current densities above 50,000 amperes per square centimeter, electromigration accelerates vacancy transport directly toward the anode pillar interface. Under combined electrical and thermal stress, even 6 parts per million sulfur produces catastrophic void coalescence within 500 hours. Operating under this analytical uncertainty, careful packaging buyers set procurement limits at 3 parts per million total sulfur.
Interfacial Cleavage and Joint Shear Degradation
Planar void chains degrade joint mechanical integrity. Interfacial shear strength drops abruptly. Tin consumption alters local stresses.
As individual nanometer-scale voids expand, they merge into continuous micro-crevices along the Cu/Cu3Sn boundary, severing the metallurgical bond between the intermetallic layer and the pillar.
Planar vacancy coalescence transforms solid metallurgical bonds into porous interfacial planes that fracture under minimal mechanical shock.
Shear tests conducted according to standard test conditions reveal a distinct transition in failure modes. Sound microbump joints exhibit ductile shear failure through the bulk solder cap. Joints containing Kirkendall void networks exhibit sudden, low-energy brittle cleavage along the Cu/Cu3Sn boundary at shear strengths below 15 megapascals.
The omission of strict impurity controls in electroplating chemistry produces finished multi-die packages that fracture during thermal cycling, board assembly surface-mount reflow, or routine drop testing, generating zero-yield manufacturing lots across backend packaging lines.
Assay
Physical verification of submicron interfacial voids presents distinct metrology challenges. Acoustic scans miss submicron pores. Thermal bakes accelerate atomic displacement.
Conventional non-destructive techniques lack the spatial resolution needed to evaluate microbump integrity beneath thick silicon dies. Inspecting microbumps demands destructive cross-sectional preparations combined with advanced electron beam instruments.
Can Acoustic Microimaging Resolve Microbump Cavities?
Scanning acoustic microscopy relies on acoustic impedance mismatches to identify internal delamination. Transducers operating at 230 to 300 megahertz achieve lateral resolutions near 12 micrometers under immersion conditions. Kirkendall voids measure between 50 nanometers and 400 nanometers in diameter during early and intermediate nucleation stages.
These cavity dimensions sit two orders of magnitude below acoustic resolution thresholds. Acoustic scans confirm gross interfacial separation only after the joint has already completely detached.
High-resolution cross-sectional examination requires focused ion beam trenching or chemical mechanical polishing followed by field-emission scanning electron microscopy. Polishing microbumps without introducing mechanical smearing demands diamond suspensions down to 50 nanometers followed by broad ion beam milling. Cross-sectional analysis confirms interfacial detachment.
Broad ion beam milling removes disturbed surface layers, exposing pristine void cavities along the Cu/Cu3Sn interface without artificial hole creation.
| Metrology Method | Spatial Resolution | Impurity Sensitivity | Destructive State | Inspection Throughput |
|---|---|---|---|---|
| C-Mode Acoustic Microscopy | 10–15 μm | None | Non-destructive | 5 wafers/hour |
| High-Resolution X-ray Micro-CT | 300–500 nm | None | Non-destructive | 1 bump/4 hours |
| FIB-SEM Cross-Sectioning | 1–2 nm | EDS: 0.1 wt% | Destructive | 3 bumps/day |
| Time-of-Flight SIMS | 50 nm (depth) | 0.01 ppm | Destructive | 2 dies/day |
| Aberration-Corrected STEM | 0.1 nm | EDS/EELS: atomic | Destructive | 1 sample/week |
Thermal Storage Reliability Qualification Boundaries
Reliability engineering protocols evaluate microbump susceptibility to Kirkendall voiding through accelerated thermal stress. JESD22-A103 High Temperature Storage Life conditions expose test vehicles to 150 degrees Celsius for intervals of 500, 1,000, and 1,500 hours. Post-stress evaluation pairs electrical resistance tracking with mechanical ball shear tests per JESD22-B117 guidelines.
- High-speed shear testing applies shear ram speeds of 100 millimeters per second to detect brittle interfacial failure modes.
- Four-point Kelvin resistance probing captures resistance shifts exceeding 10 percent across individual daisy-chain microbump networks.
- Secondary ion mass spectrometry profiling quantifies sulfur, carbon, and chlorine counts across incoming copper plating lots.
- Focused ion beam trench verification cross-sections suspicious joints displaying resistance drift to confirm vacancy coalescence along intermetallic borders.
Acoustic and electrical testing alone fail to identify incipient void networks that remain mechanically intact prior to board integration. Plating facilities relying exclusively on non-destructive scans release compromised lots into customer assembly flows.
Failure to specify secondary ion mass spectrometry in the incoming copper plating qualification standard permits sulfur concentrations exceeding thirty parts per million to pass routine wet bench inspections.
Standard procurement documentation incorporating IPC-9701 and JEDEC JESD22 standards binds suppliers to specific thermal storage durations, yet buyers frequently neglect to define acceptable interfacial void area fractions. Inserting a contract clause restricting maximum void length to less than 15 percent of total joint width across any polished cross-section forces OSAT foundries to disqualify compromised copper chemistry prior to package encapsulation.
Dispute
Commercial fallout from microbump fracture lands on engineering and legal teams with severe commercial friction. Rework costs multiply across assemblies. Contaminated chemistry invalidates production lots.
Brittle microbump fractures cause line shutdowns. Secondary ion mass spectrometry confirms sulfur. When multi-chip modules fail system-level qualification testing after board assembly, packaging sub-contractors and wafer foundries trade blame over metallurgical mechanics.
Commercial Warranty Allocation and Plating Line Audits
Foundries operating copper plating lines claim that Kirkendall voiding represents an inevitable metallurgical property of the copper-tin system governed by Fickian diffusion. They argue that customer board-level assembly reflow profiles, specifically peak temperatures exceeding 250 degrees Celsius and excessive liquidus dwell times, drove excessive intermetallic compound growth. Outsourced assembly and test providers blame substrate surface finishes, claiming that nickel-gold or immersion tin metallization on the receiving board destabilized the joint.
The buyer counters by presenting secondary ion mass spectrometry depth profiles demonstrating sulfur contamination above 20 parts per million within the electroplated copper pillar. Chemical impurity incorporation during plating represents an uncontrolled process parameter governed solely by the wafer fab. When interposer packages scrap out at costs exceeding 800 dollars per unit, financial liability hinges on whether the failure originated from assembly reflow thermal budgets or chemical contamination introduced in the plating tank.
Auditing the wafer plating line reveals the operational truth behind contamination spikes. Plating tank maintenance logs often show chemical dosing delays, worn carbon filtration packs, and extended bath operating lifetimes aimed at reducing chemical disposal expenses. Technicians operating wet benches under yield pressure occasionally increase brightener dosing to mask surface roughness, inadvertently saturating the copper deposit with sulfur breakdown products.
Engineering agreements that leave impurity thresholds undefined transfer full financial liability to the buyer once wafers clear initial electrical test gates. Chemical cleanliness at the electroplating tank governs long-term joint survival far more decisively than minor adjustments to assembly reflow temperature profiles.