Interfacial Intermetallic Growth and Void Mechanics in Soldering

Foil

The reaction between liquid solder and the printed circuit board substrate forms the mechanical and electrical foundation of every surface mount assembly. During reflow, as molten tin-rich solder touches the copper base plate, copper rapidly dissolves into the liquid alloy to initiate wetting. This dissolution immediately nucleates copper-tin intermetallic compounds at the interface, dominated initially by eta-phase copper-six-tin-five.

Whether the resulting joint survives operational mechanical shock or detaches early depends on the continuity, stoichiometry, and morphology of this primary intermetallic layer. Because copper diffuses faster than tin, this inherent directional asymmetry drives how the bond evolves structurally from the moment of liquid contact.

Assembly lines in Shenzhen and Dongguan frequently run reflow profiles tuned for speed instead of metallurgical performance. Peak temperatures exceeding two hundred and forty-five degrees Celsius thicken the initial intermetallic layer beyond acceptable limits while the solder is still liquid. That produces a coarse, scallop-shaped eta-phase boundary that invites structural failure.

Reliability requires a continuous intermetallic layer, but one thin enough to prevent brittle cleavage. In practice, technicians sometimes drop peak reflow temperatures to cover for poor flux activity, leaving non-wetting pockets and uneven intermetallic coverage across large ground plane pads.

Solder joint reliability depends on the formation of a continuous interfacial intermetallic layer that remains thin enough to prevent brittle cleavage.

The surface finish applied over the copper foil controls early growth kinetics and phase composition. Organic Solderability Preservatives allow SAC305 solder to react directly with bare copper, forming a predictable copper-six-tin-five layer. Electroless Nickel Immersion Gold places a nickel barrier over the copper to suppress diffusion, shifting the reaction toward nickel-three-tin-four and ternary copper-nickel-tin phases.

During reflow, phosphorus in the electroless nickel plating concentrates at the interface; if liquid dwell times run too short or too long, this phosphorus-rich layer becomes prone to brittle failure.

Initial Intermetallic Formation during Liquid Phase Solder Wetting

The liquid-solid reaction moves through dissolution, saturation, and crystallization over a forty-five to seventy-five second window above liquidus. Within this timeframe, the molten alloy dissolves copper from the substrate until the nearby liquid layer saturates. Eta-phase copper-six-tin-five crystals then nucleate directly on the solid copper face, growing outward into the liquid solder as scallops.

The channels between these scallops leave open paths for liquid solder to contact the raw copper underneath, keeping copper dissolution active as long as the alloy stays above liquidus.

Reflow timing directly sets layer thickness. Pushing liquid dwell time beyond ninety seconds coarsens the scallops and drives total intermetallic thickness past two micrometers before cooling begins. Solidification freezes the liquid channels between scallops into bulk solder, but the boundary connecting the intermetallic scallops to the copper substrate stays a high-energy interface that concentrates internal stress during thermal contraction.

Cooling rates right after peak reflow set the final crystal size and grain boundary density. Cooling faster than two degrees Celsius per second freezes the scalloped matrix into a fine distribution, minimizing localized stress points. Slow cooling lets the grains coarsen, creating large intermetallic structures that give micro-cracks a clean path to propagate through under impact.

Metallurgical Interactions across Bare Copper and Electroless Nickel Finishes

Direct bonding to bare copper yields a single copper-six-tin-five layer during reflow. The secondary phase, epsilon-phase copper-three-tin, doesn’t form in meaningful quantities during the brief liquid window of a standard reflow profile; its nucleation takes sustained thermal exposure and solid-state diffusion. While direct copper joints offer predictable thermal conductivity and low initial electrical resistance, they remain vulnerable to later solid-state aging.

Electroless Nickel Immersion Gold changes this by depositing a three-to-five-micrometer nickel barrier over the copper trace. The flash gold layer dissolves into the liquid solder within milliseconds, exposing the nickel underneath. Because nickel reacts much slower with molten tin than copper does, it yields a thinner nickel-three-tin-four intermetallic layer.

This barrier keeps the underlying copper intact, preserving the structural definition of ultra-fine-pitch array pads.

The drawback to this barrier is phosphorus accumulation. Electroless nickel deposits carry seven to eleven percent phosphorus by weight. As nickel reacts with tin to form nickel-three-tin-four, excess phosphorus gets rejected from the intermetallic lattice and builds up directly behind the reaction front, forming a nickel-phosphorus layer with a Ni3P phase.

This localized phosphorus concentration creates a brittle zone prone to black pad defects and sudden detachment under shock.

Choosing a surface finish comes down to balancing first-pass assembly yield against long-term durability under thermal and mechanical stress.

• Organic Solderability Preservatives offer a flat surface profile well suited for high-density ball grid arrays, though multi-pass reflow requires strict thermal control to prevent the bare copper from oxidizing early.
• Electroless Nickel Immersion Gold provides strong corrosion resistance and long shelf life, but demands tight bath chemistry control to prevent high-phosphorus embrittlement at the nickel interface.
• Immersion Silver Finish gives low-resistance contact pads, but remains vulnerable to atmospheric tarnishing and creeping corrosion in sulfur-heavy environments.
• Immersion Tin Coatings enable fast initial wetting on mid-pitch components, though extended storage increases the risk of solid-state whisker growth.

Line audits across Huizhou manufacturing plants show that board wetting delays frequently stem from chemical bath exhaustion during finish deposition rather than incoming copper oxidation.

Growth

Solid-state intermetallic growth continues long after the joint cools and exits the reflow oven. Ambient heat during burn-in testing, warm storage conditions, and normal power-on operations keeps atomic diffusion active across the interface. Over time, this post-reflow growth alters the physical nature of the joint, converting ductile solder into brittle crystalline phases.

High operating temperatures accelerate the transformation, leaving the interface to carry the structural load.

Under sustained thermal exposure, the primary copper-six-tin-five phase reacts with the copper substrate beneath it to form epsilon-phase copper-three-tin. This secondary intermetallic nucleates directly between the copper base and the copper-six-tin-five layer. Copper-three-tin is harder, less conductive, and far less ductile than the primary eta phase.

As it thickens, overall interfacial toughness drops sharply, leaving the bond susceptible to mechanical shock.

Isothermal aging at 125 degrees Celsius doubles the thickness of the embrittling copper-three-tin phase within three hundred hours.

Thermal qualification runs track layer growth weekly to catch structural drift before mass production lots leave the plant. Temperature settings require verification via calibrated external probes attached right to test boards. Uncontrolled storage in humid, high-ambient regions like Vietnam or southern China accelerates this phase transformation well before boards reach field deployment.

Solid State Diffusion Mechanics and Epsilon Phase Conversion

Solid-state intermetallic growth relies on volume and grain boundary diffusion. Copper atoms migrate rapidly into the tin matrix while tin atoms move back toward the substrate, but copper diffuses into tin orders of magnitude faster than tin diffuses into copper. This directional imbalance consumes the underlying copper substrate and drives phase shifts directly at the interface.

Forming copper-three-tin requires copper atoms to continuously migrate through the existing copper-six-tin-five layer to the tin-rich bulk solder interface, while tin moves in reverse toward the substrate. Above eighty degrees Celsius, this reaction moves fast enough to produce measurable layer growth week over week.

Growth kinetics follow a parabolic curve, with layer thickness increasing relative to the square root of exposure time. Storage tests at one hundred and fifty degrees Celsius show copper-three-tin expanding rapidly early on, passing two micrometers in thickness after five hundred hours. By that point, total intermetallic thickness across all phases routinely exceeds five micrometers ~ a threshold marked by a sharp loss in dynamic shear strength.

Thermal Acceleration and Long Term Storage Exposure Limits

Measuring solid-state intermetallic growth requires careful metallographic inspection on samples prepared in a controlled lab setting.

1. Section the board assembly along the centerline of the target solder joints using a high-precision diamond wheel saw under liquid coolant.
2. Mount the cut sample in clear epoxy resin and cold-cure for eight hours to avoid heat from exothermic hot-mounting compounds.
3. Grind the mounted specimen using silicon carbide papers from four-hundred to four-thousand grit under a steady water stream.
4. Polish the cross-section down to one-quarter micrometer using diamond suspensions on low-nap cloth until surface scratches clear at one-hundred-times optical magnification.
5. Briefly etch the polished surface with an ammonium hydroxide and hydrogen peroxide solution to highlight grain boundaries and phase lines under electron microscopy.
6. Measure intermetallic layer thickness across ten standardized points using scanning electron microscopy to calculate average phase growth and standard deviation.

The difference in activation energy between copper-six-tin-five and copper-three-tin explains why high-temperature burn-in testing selectively thickens the brittle copper-three-tin phase. In the field, hardware operating inside hot enclosures undergoes steady structural degradation over years of service.

Nickel barrier layers slow this diffusion significantly. Placing an electroless nickel layer between copper trace and solder reduces solid-state diffusion rates by about eighty percent at standard operating temperatures. Because nickel-three-tin-four grows much slower than copper-tin intermetallics under identical thermal profiles, joint ductility holds up far longer in service.

Above seventy degrees Celsius, interfacial phase growth doubles in rate for every fifteen-degree rise in operating temperature.

Cavity

Voids inside solder joints and along the substrate interface remain a persistent reliability risk in surface mount manufacturing. They degrade thermal dissipation paths, concentrate local mechanical stress, and serve as initiation sites for fatigue cracks. While bulk macro-voids stem mostly from flux volatiles outgassing during reflow, interfacial micro-voids form at the atomic scale as vacancies accumulate from asymmetric diffusion rates.

Kirkendall voids form specifically within the copper-three-tin intermetallic or right along its interface with the copper substrate. Because copper migrates out into the copper-six-tin-five layer faster than tin diffuses back, vacancies accumulate in the copper matrix behind the reaction front. Under sustained thermal stress, these atomic vacancies gather into micro-cavities that eventually merge into continuous internal planes of weakness over hundreds of operating hours.

IPC-A-610 Class 3 limits total void area in Ball Grid Array solder spheres to twenty-five percent of the total imaged area.

Evaluating void profiles requires pairing X-ray density measurements with physical cross-sections. Factory X-ray systems quickly spot large bulk voids, but lack the spatial resolution needed to detect sub-micrometer Kirkendall voids along the substrate boundary. An assembly that looks spotless under X-ray screening can still harbor dense Kirkendall void networks ready to fail under light impact.

How Does Flux Outgassing Induce Microvoid Formation?

Liquid components in solder paste volatilize rapidly as temperatures rise during reflow. If the ramp rate exceeds two degrees Celsius per second, flux solvents boil before the solder fully melts, trapping gases underneath component bodies and within the molten alloy.

Surface tension keeps small gas bubbles from escaping the liquid solder, particularly on large ground pads or bottom-termination parts like Quad Flat No-Lead packages. Trapped flux gases accumulate right at the wetting interface where intermetallics nucleate, leaving physical gaps in the crystal matrix. While volatile-driven micro-voids differ origin-wise from atomic Kirkendall voids, both mechanisms reduce the bonded pad area available to support shear loads.

Vacuum-assisted reflow ovens curb macro-voiding by dropping chamber pressure to ten millibars while the alloy is liquid. This pressure drop expands trapped gas bubbles and forces them out of the joint before the solder freezes.

Vacancy Aggregation and Kirkendall Pore Coalescence Mechanisms

Kirkendall voiding is driven by vacancy supersaturation inside the copper-three-tin intermetallic layer. The unequal movement of copper and tin sends a net flow of vacancies toward the copper substrate; once local vacancy concentration exceeds thermodynamic equilibrium, micro-cavities start to nucleate.

Foil impurities like trace sulfur, hydrogen, or electroplating additives serve as nucleation sites for these vacancies. Electroplated copper on budget PCBs frequently contains organic brightener residues that decompose during reflow and aging, creating dense arrays of sites that speed up Kirkendall pore growth. By contrast, high-purity rolled annealed copper foils show much lower susceptibility to interfacial voiding than standard electrodeposited traces.

• Macro Voids form when flux solvents get trapped in bulk solder, measuring fifteen to one hundred micrometers across.
• Planar Micro Voids line the substrate interface due to poor surface finish deposition or organic residue contamination.
• Kirkendall Voids accumulate in the copper-three-tin layer, measuring fifty nanometers to two micrometers after thermal exposure.
• Pinhole Voids pass through thin gold finish plating, exposing copper to oxidation before solder paste printing.

As Kirkendall voids accumulate, interfacial fracture toughness drops, shifting the failure mode from ductile solder deformation to brittle cleavage right along the copper-three-tin boundary.

Standard manufacturing contracts mandate compliance with IPC-A-610 Class 3 section 8.3.5, limiting total void area across Ball Grid Array pads to twenty-five percent of total sphere area, while specifying that any single void covering more than ten percent of the pad triggers an immediate lot rejection.

Stress

Mechanical and thermal stresses across a solder joint don’t distribute evenly through its volume. Instead, load concentrates along the narrow boundary joining the solder matrix to the intermetallic layer. Because intermetallic compounds have a high Young’s modulus and low strain tolerance relative to bulk solder, this interface becomes the primary failure site under shock, vibration, and thermal cycling.

In high-strain events ~ like a drop test where a device strikes a concrete floor ~ stress waves travel through the board in microseconds. Under such rapid loading, plastic deformation in the bulk solder can’t happen fast enough to absorb the shock. That energy dumps directly into the brittle intermetallic interface, driving rapid crack nucleation and cleavage failure.

High Strain Rate Mechanical Cleavage along Intermetallic Interfaces

Drop shock resistance comes down to the condition and thickness of the interfacial intermetallic layer. High-G acceleration flexes the circuit board, generating intense tensile and shear stresses across solder joints under edge-mounted components.

Qualification of alternative finish lines in Dongguan showed zero interfacial cleavage under a fifty-microsecond impact pulse. Switching from standard ENIG to immersion silver shifted the dominant failure mode from brittle intermetallic cracking to acceptable ductile failure inside the bulk solder.

Crack propagation during high-G drops follows the path of least resistance through the multi-phase interface. On bare copper or OSP finishes, cracks usually run between the copper-three-tin and copper-six-tin-five phases, or follow the Kirkendall void line where copper-three-tin meets the substrate. On ENIG, severe impact drives cracking through the phosphorus-rich nickel-phosphorus layer, shearing the solder pad cleanly off the board.

When investigating drop-shock failures, quality teams use structured decision trees to separate material defects from reflow profile issues.

1. Locate the failure via electrical continuity testing to pinpoint the exact pin or array ball.
2. Run non-destructive X-ray inspection to check for trace bridging, major bulk voiding, or substrate delamination.
3. Cross-section the failed joint along its primary stress axis, keeping the cut planar through the exact center of the pad.
4. Examine the failure path under scanning electron microscopy to verify whether fracture occurred in bulk solder, intermetallic layers, or at the copper trace interface.
5. Etch the section to expose phase boundaries and measure intermetallic thickness and Kirkendall void density along the crack line.
6. Review reflow thermal logs to verify peak temperature, time above liquidus, and cooling rate for that production run.
7. Classify the failure as process-induced embrittlement if intermetallic thickness exceeds three micrometers, or as mechanical overload if the fracture shows ductile dimpling in bulk solder.

Systemic drop-test failures point to structural degradation along the interface rather than isolated assembly defects.

Board Level Thermal Shock and Isothermal Fatigue Propagation

Thermal cycling introduces fatigue driven by coefficient of thermal expansion mismatches between silicon dies, package substrates, solder, and FR-4 circuit boards. As ambient temperatures swing from minus forty to one hundred and twenty-five degrees Celsius, these expansion differences create cyclic shear strains across every solder joint.

Unlike sudden drop shock, thermal fatigue acts through slow creep-fatigue interactions inside the solder matrix. Over hundreds of temperature cycles, plastic strain builds up at the corners of the joint. Solder grains recrystallize and soften the matrix near the intermetallic boundary, allowing cracks to initiate in these high-strain corners and travel inward along the interface.

Intermetallic growth during thermal cycling accelerates this crack propagation further. As the brittle intermetallic zone takes up more of the joint volume, the remaining ductile solder thins out, concentrating cyclic strain into an even narrower band.

Will switching to lower-temperature bismuth-bearing solders suppress intermetallic growth without causing microstructural phase separation during long-term thermal cycling?

Margin

Interfacial degradation, voiding, and excessive intermetallic growth translate directly into yield loss, warranty claims, and rework expense. Failing to control interface chemistry at the board vendor or SMT line pushes latent defects into field deployment, where field repairs cost orders of magnitude more than factory rework. Managing this risk requires setting clear quantitative inspection protocols and commercial chargeback terms before high-volume production starts.

Distance distorts quality feedback loops. When South China assembly plants ship completed boards to Western distribution hubs, three to six weeks pass in transit before final system integration. If a lot carries excessive intermetallic growth or Kirkendall voiding from long reflow dwell times, thousands of bad boards get shipped before incoming inspection flags the failure.

Cross-section sampling yields actionable interfacial data only when cut planes pass directly through the geometric center of the pad.

Effective supply contracts are written around metallographic cross-sections instead of surface X-ray scans. Automated optical and inline X-ray systems spot placement errors and gross voiding, but confirming interfacial phase thickness requires destructive lab sectioning. Building mandatory destructive sampling quotas directly into supplier quality agreements protects against widespread field failures.

Inspection Economics across Non Destructive X Ray and Metallographic Cut Planes

Choosing between inline non-destructive testing and offline destructive metallography comes down to unit inspection costs versus detection limits. Automated X-ray inspects every joint in real time and calculates void percentages at low cost per board, but it remains completely blind to intermetallic composition, Kirkendall void networks, and phosphorus enrichment.

Destructive metallography gives clear visual access to the interface, allowing micrometer-level measurement of phase boundaries and void distribution. However, it requires specialized lab tools, skilled technicians, and sacrificing finished product samples.

A balanced quality assurance program puts roughly ninety percent of screening resources into inline 2D X-ray to monitor void volume, paired with weekly destructive cross-section sampling to track intermetallic growth kinetics.

Commercial Chargeback Structures for Latent Interfacial Failure Modes

Holding suppliers accountable for latent intermetallic failures requires explicit physical thresholds written into the supply agreement. Standard warranties cover assembly defects found during initial test, but disclaim failures occurring after thirty days. Because intermetallic growth and Kirkendall voiding take months to manifest in the field, they frequently spark contractual disputes over root cause attribution.

Contractual clauses need to tie supplier liability directly to measurable metallurgical criteria rather than broad operational performance claims.

If cross-sectional analysis of production samples shows an average combined intermetallic thickness exceeding two-point-five micrometers immediately after reflow, or if total Kirkendall void density along the copper-three-tin interface exceeds five voids per ten linear micrometers, the lot faces immediate rejection at the supplier’s expense.

Enforcing these rules requires clear sampling procedures, designated independent testing labs, and mandatory chargeback schedules covering scrap, freight, and re-qualification costs.

A Ningbo factory shipping component lots without mandatory cross-sectional intermetallic audits after line maintenance highlights how unverified reflow profiles can trigger sudden air freight and qualification costs.