Lead-Free Intermetallic Growth Control in Surface Mount Electronics

Layer

Cross-section polishers reveal the structural boundary at five hundred times magnification within twenty minutes of line termination. Solder pads exposed to liquid SAC305 (96.5 percent tin, 3.0 percent silver, 0.5 percent copper) precipitate an initial scallop-shaped eta-phase Cu6Sn5 intermetallic compound along the bare copper interface. Molten tin aggressively leaches copper from the board pad during the liquid phase of reflow.

Copper dissolves at six microns per minute. This chemical reaction consumes base copper to produce the intermetallic boundary necessary for joint adhesion. Excessive growth during assembly transforms a ductile mechanical attachment into a brittle fracture zone prone to shear failure during mechanical handling.

Solid-state aging begins immediately as the joint cools below the liquidus point of 217 degrees Celsius. A secondary, copper-rich epsilon-phase Cu3Sn layer nucleates directly beneath the Cu6Sn5 phase, positioned between the scallop crystals and the base copper substrate. This planar compound grows by drawing copper atoms upward via lattice and grain-boundary diffusion.

Because copper diffuses through Cu3Sn into Cu6Sn5 significantly faster than tin diffuses downward toward the copper pad, a vacancy flux moves toward the copper interface. Vacancies coalesce into micro-voids along the Cu3Sn to copper boundary. These Kirkendall voids undermine the physical anchor of the surface mount joint.

A joint with excessive intermetallic growth fractures under drop shock before the laminate yields.

The initial thickness of the dual-phase compound immediately following the first reflow cycle dictates long-term survival in operating environments. Initial total intermetallic thickness must measure between 0.8 and 1.5 microns. When the total compound thickness exceeds 4.0 microns, brittle interfacial fracture rates rise sharply under board-level drop testing.

The activation energy for Cu6Sn5 growth during solid-state aging ranges between 0.78 and 0.85 electron-volts, derived from Arrhenius models of isothermal aging at 125 to 170 degrees Celsius across 500-hour coupons. This activation energy shifts upward when the copper substrate possesses microcrystalline rather than columnar grain structures, because grain boundaries accelerate copper migration into the solder matrix.

• Scallop coarsening occurs when extended time above liquidus allows Cu6Sn5 crystals to ripen into irregular nodules exceeding three microns in height.
• Planar Cu3Sn growth develops during thermal exposure above one hundred degrees Celsius, consuming the base metal.
• Kirkendall micro-cavitation concentrates structural vacancies directly adjacent to the underlying copper pad boundary.
• Interfacial delamination propagates along vacancy networks when boards experience shock during automated depaneling or casing assembly.

SMT quality managers in coastal contract plants frequently maintain that thick intermetallic layers prove thermal profile adequacy, asserting that prominent compound fillets demonstrate complete wetting across oxidized component leads.

Chemistry

Surface finishes deposited onto PCB landing pads govern the metallurgy of the initial liquid-solid boundary. Bare copper protected by Organic Solderability Preservatives produces the standard binary Cu-Sn reaction system. Electroless Nickel Immersion Gold introduces a barrier layer that suppresses copper migration entirely.

The nickel barrier layer, deposited with seven to nine weight percent phosphorus, shifts the interfacial reaction to form ternary (Cu,Ni)6Sn5 and binary Ni3Sn4 compounds. Liquid solder leaches the thin immersion gold layer within one second of contact, dispersing gold atoms into the bulk solder matrix where concentrations above three weight percent generate brittle AuSn4 needle-shaped crystals.

Electroless Nickel Electroless Palladium Immersion Gold incorporates a chemical palladium buffer between the nickel and gold deposits. The palladium layer, measuring 0.05 to 0.15 microns in thickness, slows the dissolution rate of nickel into molten solder while preventing galvanic hyper-corrosion of the nickel plate during immersion gold processing. During reflow, palladium dissolves into the molten SAC alloy, allowing a stable, micro-crystalline (Pd,Ni)Sn4 or (Cu,Ni)6Sn5 compound to anchor the joint without forming the brittle continuous Ni3Sn4 plate characteristic of degraded ENIG finishes.

The exact threshold for phosphorus concentration causing catastrophic black pad defect formation is reported between 9.5 and 11.0 weight percent within the nickel deposit. Uneven chemical displacement during immersion gold processing leaves localized hyper-corrosion crevices along the nickel grain boundaries that X-ray fluorescence inspection fails to detect. Under this analytical uncertainty, procurement teams require cross-sectional backscatter scanning electron microscopy on coupon strips pulled from every plating panel run rather than accepting manufacturer bath titration logs.

IPC-4552 specifies an absolute minimum nickel thickness of three microns to prevent copper diffusion into the functional joint boundary.

Doping the solder alloy with minor elemental additions suppresses intermetallic growth without requiring capital investment in PCB surface metallurgy. Adding 0.05 weight percent nickel to SAC305 stabilizes the hexagonal crystal lattice of Cu6Sn5, preventing the volumetric contraction associated with the polymorphic phase transformation from hexagonal to monoclinic crystal structures upon cooling. Small additions of cobalt or bismuth achieve comparable restraint on atomic mobility.

Cobalt limits copper dissolution into the liquid solder bath. Bismuth alters atomic migration paths along grain boundaries, lowering diffusion rates during thermal exposure cycles.

1. The quality engineer verifies the certificate of analysis for incoming bare boards, logging the nickel plating bath phosphorus concentration against the purchase order limits.
2. The laboratory micro-sections five coupon pads per panel, measuring the gold and palladium deposition depths using cross-sectional transmission electron microscopy.
3. The SMT process engineer runs a trial board through the standard thermal recipe, cutting the processed joints within two hours of cooling.
4. The technician polishes the cut joints with colloidal silica, etching the grain structure using a five percent nitric acid solution.
5. The metallurgical auditor inspects the intermetallic layer thickness across twenty ball grid array joints, rejecting lots exceeding 1.8 microns initial thickness.

Purchase contracts specifying IPC-A-610 Class 3 inspection criteria mandate continuous exclusion of interfacial gold embrittlement by restricting total gold volume in the joint below three percent of bulk solder weight.

Profile

Thermal ovens transfer heat into surface mount components through forced convection across eight to twelve discrete heating zones. Peak temperature and Time Above Liquidus control the reaction rate between tin and substrate metallization. SAC305 solder melts at 217 degrees Celsius.

Process windows target a peak temperature between 235 and 245 degrees Celsius across the PCB assembly. Excessive peak temperatures accelerate copper dissolution rates exponentially. Peak temperatures exceeding 250 degrees Celsius double copper consumption rates compared to operations run at 238 degrees Celsius.

Does Nickel Barrier Plating Prevent Kirkendall Voiding?

Electroless nickel deposits halt copper migration by establishing an insoluble physical barrier between base copper and molten tin. Nickel does not eliminate solid-state void formation entirely. During reflow, nickel reacts with tin to create Ni3Sn4, rejecting phosphorus into the underlying unreacted nickel layer.

This process forms a phosphorus-rich Ni3P layer that exhibits high internal tensile stress. Repeated thermal cycling drives micro-void formation along the Ni3P to Ni-P boundary. Nickel finishes replace copper Kirkendall voiding with phosphorus-induced interfacial embrittlement when plating conditions drift outside chemistry controls.

Liquid solder duration dictates the physical geometry of the intermetallic boundary layer. The standard qualified operating window maintains Time Above Liquidus between 45 and 75 seconds. Extending dwell time past 90 seconds creates large, elongated Cu6Sn5 scallops protruding deeply into the solder joint volume.

These sharp crystalline protrusions serve as local stress concentrators during mechanical vibration. Thermal profilers carrying ten thermocouple channels track thermal variance across dense ball grid arrays and light passive chips simultaneously.

A thirty-second increase in time above liquidus enlarges intermetallic thickness by sixty percent on standard copper lands.

Thermal accumulation dynamics resemble continuous annealing operations in wire rod production where line velocity shifts determine microstructural precipitate spacing. When thermal energy accumulates unchecked during sequential manufacturing stages, atomic migration continues unchecked. Double-sided surface mount processing subjects the first-pass solder joints to a second reflow cycle when the inverted board passes through the oven to secure reverse-side components.

The secondary cycle liquefies or thermally stresses the previously formed joint, driving further compound thickening. Secondary reflow cycles increase total intermetallic thickness by forty to seventy percent over initial values, consuming another 0.8 microns of substrate copper.

• Zone temperature drift occurs when defective heating elements fail to maintain set temperatures within two degrees Celsius.
• Conveyor speed jitter alters transit time through heating chambers, stretching dwell time beyond calibrated limits.
• Imbalanced thermal mass pulls heat away from fine-pitch components while over-heating adjacent high-mass power inductors.
• Exhaust extraction variance destabilizes oven convection currents, producing uneven intermetallic morphology across the process panel width.

A fast cooling ramp produces fine, uniform intermetallic crystal structures along the substrate interface.

Shear

Destructive mechanical testing isolates the structural consequences of excessive boundary layer growth. High-speed ball shear testing, conducted per JEDEC JESD22-B117A, strikes component solder spheres at velocities ranging from 0.1 to 1.0 meters per second. Solder joints shear under twelve megapascals.

At low test speeds, failure mechanisms localize within the ductile bulk solder, displaying extensive plastic deformation and tearing. When test velocities increase to 1.0 meter per second to simulate board-level drop events, stress concentrates directly at the intermetallic interface.

Which Cooling Rate Retards Intermetallic Compound Thickening?

Cooling ramps between 2.5 and 4.0 degrees Celsius per second suppress coarse crystalline growth effectively. Slower cooling at 1.0 degree per second extends the liquid-solid phase boundary residence, promoting thick dendritic Cu6Sn5 growth. Cooling rates exceeding 5.0 degrees Celsius per second crack fragile ceramic chip capacitors through thermal shock.

Controlled rapid cooling within the 3.0 to 4.0 degrees window limits the initial intermetallic boundary layer to sub-micron dimensions while yielding a fine-grained bulk solder matrix.

Thermal shock accelerates brittle interfacial fracture. High-temperature storage conditioning at 125 degrees Celsius for 1000 hours simulates operational thermal aging. The test data demonstrates an inverse relationship between aging duration and fracture energy absorption.

As the intermetallic boundary thickens from 1.1 microns to 5.2 microns, brittle cleavage fractures replace ductile bulk shear, dropping impact energy absorption by eighty-five percent. Kirkendall micro-voids along the Cu3Sn interface serve as propagation paths for high-speed impact cracks.

Impact failure rates correlate directly with the volumetric growth of the planar Cu3Sn phase beneath the scallop crystals.

Destructive ball pull testing per JEDEC JESD22-B115 provides complementary failure data by applying vertical tensile stress to individual joints. Joints exhibiting brittle interfacial fracture shed pads completely from the component body, leaving flat, un-wetted intermetallic surfaces exposed. Scanning electron microscope energy-dispersive X-ray spectroscopy across these fracture surfaces identifies whether the crack traversed the Cu6Sn5-to-solder interface, the Cu6Sn5-to-Cu3Sn boundary, or the Cu3Sn-to-copper pad junction.

Cleavage along the Cu3Sn-to-copper boundary confirms vacancy coalescing caused by thermal over-processing.

Engineering departments dispute whether micro-alloying additions can permanently halt Kirkendall void formation under sustained thermal operating environments exceeding one hundred degrees Celsius or merely delay mechanical decoupling past the expiration of standard consumer warranty intervals.

Penalty

Defects rooted in intermetallic overgrowth escape standard automated optical inspection and automated X-ray inspection. These scanning systems check joint presence, volume, bridging, and gross alignment. An over-aged joint with a six-micron intermetallic boundary looks identical to a compliant joint with a one-micron layer on an optical image or transmission X-ray radiograph.

Brittle assemblies clear factory functional testing without displaying electrical anomalies. The physical detachment surfaces weeks later when products experience drops, transportation vibration, or cyclic operating temperatures in end-user applications.

A manufacturing defect that escapes line audits to trigger field failures carries significant commercial liabilities. Product recalls for safety-critical or high-reliability electronic assemblies involve field extraction labor, reverse logistics, freight expediting, customer service administrative overhead, and complete assembly scrapping. When failure analysis isolates the root cause to brittle interfacial fracturing driven by excessive time above liquidus or out-of-specification board plating chemistry, contract liabilities shift entirely to the manufacturing supplier under warranty indemnity terms.

Suppliers absorb secondary sorting labor costs. Recovering commercial losses from offshore contract manufacturers requires unambiguous inspection criteria built into original supply agreements. Standard manufacturing agreements must define precise intermetallic thickness windows, mandating destructive micro-sectioning of five production samples per five thousand board units.

When destructive sampling demonstrates boundary layers exceeding 2.5 microns directly off the SMT line, the customer retains contractual authority to quarantine the entire batch at the supplier factory gate.

Allowing unmonitored reflow lines to run uninspected shifts transforms component assemblies into latent field liabilities, resulting in catastrophic commercial warranty exposures when thousands of brittle joints fracture under everyday mechanical transit loads.