Meaning
Physical evaluation of the impact resistance of surface mount components determines how a device handles the deceleration of a fall. Most facilities conduct board level drop testing according to the jesd22-b111 standard to ensure that solder joints remain intact during transport and consumer use. The procedure specifically measures the durability of the interconnects rather than the housing of the device.
Impact Response
High gravitational force pulses are applied to a test vehicle to simulate the shock of hitting a hard surface. During board level drop testing, the peak acceleration and pulse duration are controlled by the height of the fall and the material of the strike plate. This sudden energy transfer causes the circuit board to flex, creating a combination of tension and shear at the component corners.
Failure Mode
Cracking usually occurs at the interface between the solder ball and the copper pad on the substrate. Engineers monitor board level drop testing through real time electrical resistance checks that detect the exact moment a circuit opens. These failures are often attributed to the formation of brittle intermetallic compounds that cannot absorb the energy of the impact.
Qualification Standard
Batch acceptance depends on the number of drops a design survives before the electrical resistance exceeds a predefined limit. Standardised board level drop testing allows designers to compare the performance of different solder alloys and pad finishes. Final reports document the statistical distribution of failures to predict the field performance of the product.
