Meaning
Real part of the admittance measured in a metal-oxide-semiconductor structure reflects the energy dissipation caused by the capture and emission of carriers at interface states. Parallel conductance is a frequency-dependent value that provides a signature of the defect distribution within the device. It is typically extracted from raw impedance data by subtracting the effects of the insulating layer capacitance.
Engineers in the Chinese semiconductor industry use this parameter to perform detailed spectroscopy of interface traps.
Dielectric Loss
Fluctuations in the occupancy of electronic states at the interface lead to a loss of energy that appears as a conductive component in parallel with the capacitor. High values of parallel conductance indicate a population of traps that are active at a given bias and frequency. This loss mechanism is distinct from the leakage current flowing through the oxide itself.
The peak of the conductance curve shifts as the gate voltage changes the surface potential.
Extraction Process
Calculation of the loss component requires an accurate model of the entire gate stack, including the series resistance of the substrate. To isolate the parallel conductance, the measured capacitance and conductance are transformed into an equivalent circuit representation. This mathematical conversion accounts for the reactance of the oxide layer.
Software tools used in automated test environments perform these calculations in real time during a frequency sweep. The resulting parallel conductance divided by the angular frequency is then plotted against frequency to find the peak that corresponds to the interface state density.
Quality Assessment
Uniformity of the interface across a large diameter wafer is evaluated by mapping the peak parallel conductance across multiple test sites. A low and narrow distribution of these values suggests a stable and high-quality oxidation process. Discrepancies between the measured data and theoretical models can reveal the presence of non-uniformities or gross defects in the fabrication.
This metric is a standard part of the reliability data package required for the commercial release of new semiconductor products.